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Searched refs:num_vcn_inst (Results 1 – 25 of 25) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c61 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) in vcn_v5_0_1_early_init()
68 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_1_early_init()
114 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_1_sw_init()
164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_1_sw_fini()
175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_1_sw_fini()
181 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_1_sw_fini()
209 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_1_hw_init()
242 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_1_hw_fini()
269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_1_suspend()
290 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_1_resume()
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H A Dvcn_v5_0_0.c100 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) in vcn_v5_0_0_early_init()
107 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_early_init()
146 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_sw_init()
225 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_sw_fini()
239 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_sw_fini()
247 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_sw_fini()
271 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_hw_init()
300 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_hw_fini()
336 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_suspend()
357 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_resume()
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H A Dvcn_v4_0_3.c118 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) in vcn_v4_0_3_early_init()
126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_early_init()
172 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_init()
259 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_fini()
272 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_fini()
280 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_fini()
374 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_hw_fini()
402 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_suspend()
423 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_resume()
1758 if (inst >= adev->vcn.num_vcn_inst) { in vcn_v4_0_3_process_interrupt()
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H A Dvcn_v4_0_5.c121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) in vcn_v4_0_5_early_init()
127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_early_init()
154 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_sw_init()
248 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_sw_fini()
265 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_sw_fini()
293 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_hw_init()
322 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_hw_fini()
358 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_suspend()
379 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_resume()
1487 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_set_unified_ring_funcs()
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H A Dvcn_v4_0.c122 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_early_init()
130 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) in vcn_v4_0_early_init()
138 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_early_init()
189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_init()
286 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()
303 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()
311 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()
340 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()
381 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_fini()
419 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_suspend()
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H A Dvcn_v2_5.c120 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_idle_work_handler()
252 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()
254 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in vcn_v2_5_early_init()
260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
277 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
303 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
458 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()
488 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()
532 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()
568 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_suspend()
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H A Dvcn_v3_0.c133 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in vcn_v3_0_early_init()
142 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_early_init()
155 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_early_init()
194 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_init()
325 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()
341 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()
374 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()
405 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()
442 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_fini()
478 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_suspend()
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H A Damdgpu_vcn.c338 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_save_vcpu_bo()
1269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_ras_late_init()
1347 if (adev->vcn.num_vcn_inst) { in amdgpu_vcn_sysfs_reset_mask_init()
1359 if (adev->vcn.num_vcn_inst) in amdgpu_vcn_sysfs_reset_mask_fini()
1379 mask = (1ULL << adev->vcn.num_vcn_inst) - 1; in amdgpu_debugfs_vcn_sched_mask_set()
1382 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_debugfs_vcn_sched_mask_set()
1403 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_debugfs_vcn_sched_mask_get()
1424 if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue) in amdgpu_debugfs_vcn_sched_mask_init()
1446 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_set_powergating_state()
H A Damdgpu_discovery.c1387 if (adev->vcn.num_vcn_inst < in amdgpu_discovery_reg_base_init()
1389 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = in amdgpu_discovery_reg_base_init()
1391 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()
1398 adev->vcn.num_vcn_inst + 1, in amdgpu_discovery_reg_base_init()
1549 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()
1749 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { in amdgpu_discovery_get_vcn_info()
1767 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { in amdgpu_discovery_get_vcn_info()
2630 adev->vcn.num_vcn_inst = 1; in amdgpu_discovery_set_ip_blocks()
2694 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
2722 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
H A Daqua_vanjaram.c67 return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst); in aqua_vanjaram_xcp_vcn_shared()
402 num_vcn = adev->vcn.num_vcn_inst; in __aqua_vanjaram_get_xcp_ip_info()
466 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; in aqua_vanjaram_get_xcp_res_info()
833 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask); in aqua_vanjaram_init_soc_config()
H A Damdgpu_vcn.h341 uint8_t num_vcn_inst; member
H A Dvcn_v1_0.c205 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v1_0_sw_init()
1959 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); in vcn_v1_0_print_ip_state()
1960 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v1_0_print_ip_state()
1992 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v1_0_dump_ip_state()
H A Dvcn_v2_0.c228 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v2_0_sw_init()
2063 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); in vcn_v2_0_print_ip_state()
2064 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_0_print_ip_state()
2096 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_0_dump_ip_state()
H A Dsoc24.c76 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc24_query_video_codecs()
H A Damdgpu_kms.c446 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
458 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
668 count = adev->vcn.num_vcn_inst; in amdgpu_info_ioctl()
H A Dsoc21.c147 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc21_query_video_codecs()
H A Dnv.c213 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs()
H A Damdgpu_debugfs.c2085 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_debugfs_init()
H A Damdgpu_ras.c383 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); in amdgpu_ras_instance_mask_check()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c799 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in smu_set_default_dpm_table()
806 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_set_default_dpm_table()
828 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in smu_set_default_dpm_table()
1284 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in smu_sw_init()
1842 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in smu_hw_init()
2047 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_hw_fini()
3077 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_read_sensor()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c1371 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v14_0_set_performance_level()
1387 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v14_0_set_performance_level()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c1833 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_performance_level()
1849 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_performance_level()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsienna_cichlid_ppt.c1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()
1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()
/linux-6.15/drivers/gpu/drm/amd/pm/
H A Damdgpu_pm.c2024 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in pp_dpm_clk_default_attr_update()
2047 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in pp_dpm_clk_default_attr_update()
H A Damdgpu_dpm.c84 (!is_vcn || adev->vcn.num_vcn_inst == 1)) { in amdgpu_dpm_set_powergating_by_smu()