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Searched refs:inst_mask (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v1_8.c58 u32 inst_mask; in mmhub_v1_8_setup_vm_pt_regs() local
79 u32 inst_mask; in mmhub_v1_8_init_gart_aperture_regs() local
129 uint32_t tmp, inst_mask; in mmhub_v1_8_init_system_aperture_regs() local
192 uint32_t tmp, inst_mask; in mmhub_v1_8_init_tlb_regs() local
325 u32 inst_mask; in mmhub_v1_8_disable_identity_aperture() local
424 u32 i, j, inst_mask; in mmhub_v1_8_program_invalidation() local
461 u32 i, j, inst_mask; in mmhub_v1_8_gart_disable() local
498 u32 tmp, inst_mask; in mmhub_v1_8_set_fault_enable_default() local
544 u32 inst_mask; in mmhub_v1_8_init() local
689 uint32_t inst_mask; in mmhub_v1_8_query_ras_error_count() local
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H A Dsdma_v4_4_2.c159 uint32_t inst_mask) in sdma_v4_4_2_inst_init_golden_registers() argument
624 uint32_t inst_mask) in sdma_v4_4_2_inst_enable() argument
985 tmp_mask = inst_mask; in sdma_v4_4_2_inst_start()
1022 tmp_mask = inst_mask; in sdma_v4_4_2_inst_start()
1544 uint32_t inst_mask; in sdma_v4_4_2_hw_init() local
1558 uint32_t inst_mask; in sdma_v4_4_2_hw_fini() local
1683 u32 inst_mask; in sdma_v4_4_2_stop_queue() local
1721 u32 inst_mask; in sdma_v4_4_2_restore_queue() local
2017 uint32_t inst_mask; in sdma_v4_4_2_set_clockgating_state() local
2488 uint32_t inst_mask; in sdma_v4_4_2_query_ras_error_count() local
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H A Damdgpu_xcp.h84 int (*prepare_suspend)(void *handle, uint32_t inst_mask);
85 int (*suspend)(void *handle, uint32_t inst_mask);
86 int (*prepare_resume)(void *handle, uint32_t inst_mask);
87 int (*resume)(void *handle, uint32_t inst_mask);
92 uint32_t inst_mask; member
167 uint32_t *inst_mask);
H A Daqua_vanjaram.c75 uint32_t inst_mask; in aqua_vanjaram_set_xcp_id() local
84 inst_mask = 1 << inst_idx; in aqua_vanjaram_set_xcp_id()
105 if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { in aqua_vanjaram_set_xcp_id()
264 uint32_t inst_mask) in aqua_vanjaram_populate_ip_map() argument
268 while (inst_mask) { in aqua_vanjaram_populate_ip_map()
269 i = ffs(inst_mask) - 1; in aqua_vanjaram_populate_ip_map()
271 inst_mask &= ~(1 << i); in aqua_vanjaram_populate_ip_map()
282 { VCN_HWIP, adev->vcn.inst_mask }, in aqua_vanjaram_ip_map_init()
438 ip->inst_mask = in __aqua_vanjaram_get_xcp_ip_info()
818 inst_mask >>= adev->sdma.num_inst_per_aid; in aqua_vanjaram_init_soc_config()
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H A Damdgpu_xcp.c33 int (*run_func)(void *handle, uint32_t inst_mask); in __amdgpu_xcp_run()
57 ret = run_func(xcp_mgr->adev, xcp_ip->inst_mask); in __amdgpu_xcp_run()
325 (xcp->ip[ip].inst_mask & BIT(instance))) in amdgpu_xcp_get_partition()
337 uint32_t *inst_mask) in amdgpu_xcp_get_inst_details() argument
339 if (!xcp->valid || !inst_mask || !(xcp->ip[ip].valid)) in amdgpu_xcp_get_inst_details()
342 *inst_mask = xcp->ip[ip].inst_mask; in amdgpu_xcp_get_inst_details()
H A Dgfxhub_v1_2.c641 static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t inst_mask) in gfxhub_v1_2_xcp_resume() argument
651 gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, inst_mask); in gfxhub_v1_2_xcp_resume()
654 return gfxhub_v1_2_xcc_gart_enable(adev, inst_mask); in gfxhub_v1_2_xcp_resume()
659 static int gfxhub_v1_2_xcp_suspend(void *handle, uint32_t inst_mask) in gfxhub_v1_2_xcp_suspend() argument
664 gfxhub_v1_2_xcc_gart_disable(adev, inst_mask); in gfxhub_v1_2_xcp_suspend()
H A Dnbio_v7_9.c432 u32 inst_mask; in nbio_v7_9_init_registers() local
440 inst_mask = adev->aid_mask & ~1U; in nbio_v7_9_init_registers()
441 for_each_inst(i, inst_mask) { in nbio_v7_9_init_registers()
H A Damdgpu_kms.c572 u32 count, inst_mask; in amdgpu_info_ioctl() local
626 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); in amdgpu_info_ioctl()
629 count = hweight32(inst_mask); in amdgpu_info_ioctl()
632 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); in amdgpu_info_ioctl()
635 count = hweight32(inst_mask); in amdgpu_info_ioctl()
638 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); in amdgpu_info_ioctl()
641 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; in amdgpu_info_ioctl()
644 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); in amdgpu_info_ioctl()
647 count = hweight32(inst_mask); in amdgpu_info_ioctl()
H A Damdgpu_discovery.c369 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_config_quirk()
676 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
678 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
682 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
684 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
734 adev->vcn.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
736 adev->jpeg.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
1339 adev->vcn.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1340 adev->jpeg.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1392 adev->vcn.inst_mask |= in amdgpu_discovery_reg_base_init()
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H A Damdgpu_jpeg.h137 uint16_t inst_mask; member
H A Damdgpu.h1443 #define for_each_inst(i, inst_mask) \ argument
1444 for (i = ffs(inst_mask); i-- != 0; \
1445 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
H A Damdgpu_vcn.h349 uint16_t inst_mask; member
H A Dgmc_v9_0.c2084 unsigned long inst_mask = adev->aid_mask; in gmc_v9_0_sw_init() local
2180 inst_mask <<= AMDGPU_MMHUB0(0); in gmc_v9_0_sw_init()
2181 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); in gmc_v9_0_sw_init()
H A Damdgpu_ras.c362 uint32_t mask, inst_mask = data->inject.instance_mask; in amdgpu_ras_instance_mask_check() local
365 if (num_xcc <= 1 && inst_mask) { in amdgpu_ras_instance_mask_check()
369 inst_mask); in amdgpu_ras_instance_mask_check()
386 mask = inst_mask; in amdgpu_ras_instance_mask_check()
392 if (inst_mask != data->inject.instance_mask) in amdgpu_ras_instance_mask_check()
395 inst_mask, data->inject.instance_mask); in amdgpu_ras_instance_mask_check()
H A Dgfx_v9_4_3.c4909 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) in gfx_v9_4_3_xcp_resume() argument
4918 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4923 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4931 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4941 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) in gfx_v9_4_3_xcp_suspend() argument
4946 for_each_inst(i, inst_mask) in gfx_v9_4_3_xcp_suspend()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_12_ppt.c355 u32 inst_mask; in smu_v13_0_12_get_gpu_metrics() local
452 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); in smu_v13_0_12_get_gpu_metrics()
454 for_each_inst(k, inst_mask) { in smu_v13_0_12_get_gpu_metrics()
469 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); in smu_v13_0_12_get_gpu_metrics()
471 for_each_inst(k, inst_mask) { in smu_v13_0_12_get_gpu_metrics()
H A Dsmu_v13_0_6_ppt.c2500 u32 inst_mask; in smu_v13_0_6_get_gpu_metrics() local
2641 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); in smu_v13_0_6_get_gpu_metrics()
2643 for_each_inst(k, inst_mask) { in smu_v13_0_6_get_gpu_metrics()
2660 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); in smu_v13_0_6_get_gpu_metrics()
2662 for_each_inst(k, inst_mask) { in smu_v13_0_6_get_gpu_metrics()
2910 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask) in smu_v13_0_6_reset_sdma() argument
2918 SMU_MSG_ResetSDMA, inst_mask, NULL); in smu_v13_0_6_reset_sdma()
2922 inst_mask); in smu_v13_0_6_reset_sdma()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h1379 int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask);
1644 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask);
/linux-6.15/drivers/gpu/drm/amd/pm/inc/
H A Damdgpu_dpm.h608 int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask);
/linux-6.15/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c768 int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) in amdgpu_dpm_reset_sdma() argument
777 ret = smu_reset_sdma(smu, inst_mask); in amdgpu_dpm_reset_sdma()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c3969 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) in smu_reset_sdma() argument
3974 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); in smu_reset_sdma()