| /linux-6.15/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_rlc.c | 111 dst_ptr = adev->gfx.rlc.sr_ptr; in amdgpu_gfx_rlc_init_sr()
134 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
206 (adev->gfx.ce_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
214 (adev->gfx.pfp_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
222 (adev->gfx.me_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
230 (adev->gfx.mec_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
238 (adev->gfx.mec2_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
324 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in amdgpu_gfx_rlc_init_microcode_v2_0()
334 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_0()
370 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
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| H A D | amdgpu_gfx.c | 208 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
261 adev->gfx.num_gfx_rings = in amdgpu_gfx_graphics_queue_acquire()
960 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
963 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
990 if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler) in amdgpu_gfx_poison_consumption_handler()
1008 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && in amdgpu_gfx_process_ras_data_cb()
1041 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()
1239 adev->gfx.me_fw->data; in amdgpu_gfx_cp_init_microcode()
1249 adev->gfx.me_fw->data; in amdgpu_gfx_cp_init_microcode()
1260 adev->gfx.me_fw->data; in amdgpu_gfx_cp_init_microcode()
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| H A D | gfx_v11_0.c | 785 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { in gfx_v11_0_init_microcode()
1544 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v11_0_alloc_ip_dump()
1557 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v11_0_alloc_ip_dump()
2154 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v11_0_init_csb()
2344 if (!adev->gfx.rlc_fw) in gfx_v11_0_rlc_load_microcode()
2667 adev->gfx.me_fw->data; in gfx_v11_0_config_me_cache_rs64()
2875 adev->gfx.me_fw->data; in gfx_v11_0_config_gfx_rs64()
3493 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) in gfx_v11_0_cp_gfx_load_microcode()
3784 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode()
3836 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode_rs64()
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| H A D | gfx_v12_0.c | 1124 adev->gfx.me_fw->data; in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode()
1318 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v12_0_alloc_ip_dump()
1331 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v12_0_alloc_ip_dump()
1389 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, in gfx_v12_0_sw_init()
1826 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v12_0_init_csb()
1968 if (!adev->gfx.rlc_fw) in gfx_v12_0_rlc_load_microcode()
2038 adev->gfx.me_fw->data; in gfx_v12_0_config_gfx_rs64()
2161 adev->gfx.me_fw->data; in gfx_v12_0_set_me_ucode_start_addr()
2426 adev->gfx.me_fw->data; in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2565 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) in gfx_v12_0_cp_gfx_load_microcode()
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| H A D | gfx_v6_0.c | 402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()
1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
1691 adev->gfx.config.num_gpus = 1; in gfx_v6_0_constants_init()
1951 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v6_0_cp_gfx_load_microcode()
2081 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_resume()
2357 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2503 if (!adev->gfx.rlc_fw) in gfx_v6_0_rlc_resume()
3045 adev->gfx.xcc_mask = 1; in gfx_v6_0_early_init()
3088 ring = &adev->gfx.gfx_ring[i]; in gfx_v6_0_sw_init()
3092 &adev->gfx.eop_irq, in gfx_v6_0_sw_init()
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| H A D | gfx_v7_0.c | 2396 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2417 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2427 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2437 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2659 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2683 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
2742 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
3420 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
4147 adev->gfx.xcc_mask = 1; in gfx_v7_0_early_init()
4264 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
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| H A D | gfx_v8_0.c | 1097 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1142 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1149 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1162 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1169 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1201 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1816 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1928 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1933 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
3880 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v8_0_init_csb()
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| H A D | gfx_v9_0.c | 1557 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; in gfx_v9_0_init_cp_compute_microcode()
1558 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; in gfx_v9_0_init_cp_compute_microcode()
2200 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_0_alloc_ip_dump()
2333 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { in gfx_v9_0_sw_init()
2352 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], in gfx_v9_0_sw_init()
2435 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { in gfx_v9_0_sw_fini()
2746 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v9_0_init_csb()
3245 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
5929 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; in gfx_v9_0_ring_emit_reg_write_reg_wait()
7359 if (!adev->gfx.ip_dump_core || !adev->gfx.num_gfx_rings) in gfx_v9_ip_dump()
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| H A D | gfx_v9_4_3.c | 578 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; in gfx_v9_4_3_init_cp_compute_microcode()
579 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; in gfx_v9_4_3_init_cp_compute_microcode()
973 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + in gfx_v9_4_3_compute_ring_init()
1021 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_alloc_ip_dump()
1558 if (!adev->gfx.rlc_fw) in gfx_v9_4_3_xcc_rlc_load_microcode()
1713 if (!adev->gfx.mec_fw) in gfx_v9_4_3_xcc_cp_compute_load_microcode()
2153 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_xcc_kcq_fini_register()
2502 if (adev->gfx.ras && in gfx_v9_4_3_late_init()
4541 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_print()
4600 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_dump()
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| H A D | amdgpu_dev_coredump.c | 88 adev->gfx.me_feature_version, adev->gfx.me_fw_version); in amdgpu_devcoredump_fw_info()
90 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version); in amdgpu_devcoredump_fw_info()
92 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version); in amdgpu_devcoredump_fw_info()
94 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version); in amdgpu_devcoredump_fw_info()
98 adev->gfx.rlc_srlc_fw_version); in amdgpu_devcoredump_fw_info()
107 adev->gfx.rlcp_ucode_version); in amdgpu_devcoredump_fw_info()
110 adev->gfx.rlcv_ucode_version); in amdgpu_devcoredump_fw_info()
112 adev->gfx.mec_feature_version, adev->gfx.mec_fw_version); in amdgpu_devcoredump_fw_info()
114 if (adev->gfx.mec2_fw) in amdgpu_devcoredump_fw_info()
117 adev->gfx.mec2_fw_version); in amdgpu_devcoredump_fw_info()
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| H A D | gfx_v10_0.c | 4725 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v10_0_alloc_ip_dump()
4738 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v10_0_alloc_ip_dump()
5111 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
5411 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v10_0_init_csb()
5498 if (!adev->gfx.rlc_fw) in gfx_v10_0_rlc_load_microcode()
5734 adev->gfx.ce_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5744 adev->gfx.me_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
6151 adev->gfx.ce_fw->data; in gfx_v10_0_cp_gfx_load_ce_microcode()
6228 adev->gfx.me_fw->data; in gfx_v10_0_cp_gfx_load_me_microcode()
6299 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
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| H A D | amdgpu_atomfirmware.c | 832 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
833 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
836 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
837 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
839 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
841 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
850 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
851 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
854 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
871 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
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| H A D | amdgpu_kms.c | 233 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
237 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
241 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
245 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
270 fw_info->ver = adev->gfx.mec_fw_version; in amdgpu_firmware_info()
360 fw_info->ver = adev->gfx.imu_fw_version; in amdgpu_firmware_info()
390 if (adev->gfx.gfx_ring[i].sched.ready) in amdgpu_hw_ip_info()
879 adev->gfx.config.max_shader_engines; in amdgpu_info_ioctl()
884 if (adev->gfx.mcbp) in amdgpu_info_ioctl()
1363 if (adev->gfx.mcbp) { in amdgpu_driver_open_kms()
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| H A D | amdgpu_ucode.c | 888 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; in amdgpu_ucode_init_single_fw()
892 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; in amdgpu_ucode_init_single_fw()
896 ucode_addr = adev->gfx.rlc.save_restore_list_srm; in amdgpu_ucode_init_single_fw()
900 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; in amdgpu_ucode_init_single_fw()
904 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; in amdgpu_ucode_init_single_fw()
908 ucode_addr = adev->gfx.rlc.rlcp_ucode; in amdgpu_ucode_init_single_fw()
912 ucode_addr = adev->gfx.rlc.rlcv_ucode; in amdgpu_ucode_init_single_fw()
920 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; in amdgpu_ucode_init_single_fw()
924 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; in amdgpu_ucode_init_single_fw()
928 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; in amdgpu_ucode_init_single_fw()
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| H A D | imu_v12_0.c | 56 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v12_0_init_microcode()
61 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
66 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
76 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v12_0_init_microcode()
88 if (!adev->gfx.imu_fw) in imu_v12_0_load_microcode()
91 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_load_microcode()
93 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v12_0_load_microcode()
102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
104 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v12_0_load_microcode()
114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
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| H A D | imu_v11_0.c | 65 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
70 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
74 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
81 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
93 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
96 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
99 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
108 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
110 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
120 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
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| H A D | amdgpu_debugfs.c | 433 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_gprwave_read()
438 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gprwave_read()
441 if (adev->gfx.funcs->read_wave_sgprs) in amdgpu_debugfs_gprwave_read()
897 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
901 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
913 config[no_regs++] = adev->gfx.config.num_gpus; in amdgpu_debugfs_gca_config_read()
917 config[no_regs++] = adev->gfx.config.num_rbs; in amdgpu_debugfs_gca_config_read()
1091 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_wave_read()
1185 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gpr_read()
1188 if (adev->gfx.funcs->read_wave_sgprs) in amdgpu_debugfs_gpr_read()
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| H A D | amdgpu_discovery.c | 748 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1038 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1337 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1434 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
1589 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1595 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
1603 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); in amdgpu_discovery_get_gfx_info()
1610 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); in amdgpu_discovery_get_gfx_info()
1629 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); in amdgpu_discovery_get_gfx_info()
1639 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
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| H A D | amdgpu_amdkfd.c | 194 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
201 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
202 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
419 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
422 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
425 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
428 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
431 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
434 return adev->gfx.rlc_fw_version; in amdgpu_amdkfd_get_fw_version()
488 if (adev->gfx.funcs->get_gpu_clock_counter) in amdgpu_amdkfd_get_gpu_clock_counter()
[all …]
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| /linux-6.15/drivers/gpu/drm/ci/xfails/ |
| H A D | i915-amly-flakes.txt | 2 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
9 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
16 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
23 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
30 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
37 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
44 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
51 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
|
| H A D | i915-cml-flakes.txt | 2 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
9 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
16 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
23 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
|
| /linux-6.15/Documentation/ABI/testing/ |
| H A D | sysfs-driver-intel-i915-hwmon | 4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
|
| /linux-6.15/drivers/pmdomain/qcom/ |
| H A D | rpmhpd.c | 244 [SA8775P_GFX] = &gfx,
267 [RPMHPD_GFX] = &gfx,
290 [SDM670_GFX] = &gfx,
308 [SDM845_GFX] = &gfx,
366 [SM6350_GFX] = &gfx,
382 [RPMHPD_GFX] = &gfx,
400 [SM8150_GFX] = &gfx,
435 [RPMHPD_GFX] = &gfx,
454 [RPMHPD_GFX] = &gfx,
476 [RPMHPD_GFX] = &gfx,
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_crat.c | 1433 if (adev->gfx.config.gc_tcp_l1_size) { in kfd_fill_gpu_cache_info_from_gfx_config()
1448 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
1460 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1473 if (adev->gfx.config.gc_gl1c_per_sa && in kfd_fill_gpu_cache_info_from_gfx_config()
1474 adev->gfx.config.gc_gl1c_size_per_instance) { in kfd_fill_gpu_cache_info_from_gfx_config()
1476 adev->gfx.config.gc_gl1c_size_per_instance; in kfd_fill_gpu_cache_info_from_gfx_config()
1487 if (adev->gfx.config.gc_gl2c_per_gpu) { in kfd_fill_gpu_cache_info_from_gfx_config()
1520 if (adev->gfx.config.gc_tcp_size_per_cu) { in kfd_fill_gpu_cache_info_from_gfx_config_v2()
1534 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config_v2()
1544 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config_v2()
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/gpu/ |
| H A D | aspeed-gfx.txt | 6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
|