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Searched refs:PMC (Results 1 – 25 of 64) sorted by relevance

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/linux-6.15/drivers/video/fbdev/riva/
H A Dnvreg.h126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
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H A Dnv_driver.c167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
330 par->riva.PMC = in riva_common_setup()
H A Driva_hw.c1379 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1533 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1534 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1535 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1536 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1539 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
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/linux-6.15/Documentation/firmware-guide/acpi/
H A Dintel-pmc-mux.rst10 North Mux-Agent is a function of the Intel PMC firmware that is supported on
11 most Intel based platforms that have the PMC microcontroller. It's used for
16 The North Mux-Agent (aka. Intel PMC Mux Control, or just mux-agent) driver
17 communicates with the PMC microcontroller by using the PMC IPC method
31 is a separate child node under the PMC mux-agent device node. Those nodes do not
35 Scope (_SB.PCI0.PMC.MUX)
54 Scope (_SB.PCI0.PMC.MUX)
73 In order to configure the muxes behind a USB Type-C connector, the PMC firmware
80 the PMC::
117 Scope (_SB.PCI0.PMC)
/linux-6.15/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpmc.txt6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
23 is the PMC block, and the second resource is the Clock Configuration
30 resource is the PMC block interrupt.
/linux-6.15/Documentation/ABI/obsolete/
H A Dsysfs-driver-intel_pmc_bxt1 These files allow sending arbitrary IPC commands to the PMC/SCU which
10 IPC command to the PMC/SCU.
20 Northpeak through the PMC/SCU.
/linux-6.15/drivers/platform/x86/intel/pmc/
H A DKconfig7 tristate "Intel PMC Core driver"
16 tasks in the PMC in order to enable transition into the SLPS0 state.
26 - PMC quirks as needed to enable SLPS0/S0ix
/linux-6.15/Documentation/driver-api/xilinx/
H A Deemi.rst10 used by any driver to communicate with PMC(Platform Management Controller).
16 device to communicate with a power management controller (PMC) on a
19 Any driver who wants to communicate with PMC using EEMI APIs use the
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt16 - reg : shall be the control register offset from PMC base for the pll clock.
36 - enable-reg : shall be the register offset from PMC base for the enable
44 - divisor-reg : shall be the register offset from PMC base for the divisor
H A Datmel,at91rm9200-pmc.yaml7 title: Atmel Power Management Controller (PMC)
14 system and user peripheral clocks. The PMC enables/disables the clock inputs
/linux-6.15/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml7 title: Tegra Power Management Controller (PMC)
38 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
41 Consumer of PMC clock should specify the desired clock by having the
42 clock ID in its "clocks" phandle cell with PMC clock provider. See
43 include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
55 Management Unit, whose interrupt output signal is fed into the PMC. This
56 signal is optionally inverted, and then fed into the ARM GIC. The PMC is
74 description: CPU power good signal from external PMIC to PMC is enabled
185 domain on the Tegra SoC that can be power-gated by the Tegra PMC.
254 of the hardware. The PMC can be used to set pad power state and
/linux-6.15/drivers/video/fbdev/nvidia/
H A Dnv_hw.c147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
1266 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1270 NV_WR32(par->PMC, 0x170C, in NVLoadStateExt()
1525 NV_WR32(par->PMC, 0x8704, 1); in NVLoadStateExt()
1526 NV_WR32(par->PMC, 0x8140, 0); in NVLoadStateExt()
1527 NV_WR32(par->PMC, 0x8920, 0); in NVLoadStateExt()
1528 NV_WR32(par->PMC, 0x8924, 0); in NVLoadStateExt()
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H A Dnv_backlight.c57 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
70 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
/linux-6.15/drivers/platform/x86/amd/pmc/
H A DKconfig3 # AMD PMC Driver
7 tristate "AMD SoC PMC driver"
/linux-6.15/drivers/perf/
H A Dfsl_imx9_ddr_perf.c46 #define PMC(n) (0x40 + 0x18 + (0x10 * n)) macro
368 writel(0, pmu->base + PMC(counter) + 0x4); in ddr_perf_clear_counter()
369 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
371 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
381 val = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
387 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4); in ddr_perf_read_counter()
388 val_lower = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
389 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4)); in ddr_perf_read_counter()
/linux-6.15/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra30-tsensor.yaml25 Generates a signal to the PMC when the temperature reaches dangerously high
26 levels to reset the chip and sets a flag in the PMC.
/linux-6.15/Documentation/devicetree/bindings/iio/adc/
H A Dgehc,pmc-adc.yaml7 title: GE HealthCare PMC Analog to Digital Converter (ADC)
13 The GE HealthCare PMC ADC is a 16-Channel (voltage and current), 16-Bit ADC
/linux-6.15/drivers/usb/typec/mux/
H A DKconfig29 tristate "Intel PMC mux control"
35 Driver for USB muxes controlled by Intel PMC FW. Intel PMC FW can
/linux-6.15/drivers/net/can/esd/
H A DKconfig9 M.2 PCIe, CPCIserial, PMC, XMC (see https://esd.eu/en)
/linux-6.15/arch/powerpc/boot/dts/
H A Dxpedite5200_xmon.dts17 form-factor = "PMC/XMC";
108 * 6: PMC monarch indicator
109 * 7: PMC EREADY
445 /* PMC interface */
H A Dmvme5100.dts130 /* IDSEL 16 - PMC Slot 1 */
136 /* IDSEL 17 - PMC Slot 2 */
H A Dxpedite5200.dts104 * 6: PMC monarch indicator
105 * 7: PMC EREADY
442 /* PMC interface */
/linux-6.15/arch/sparc/include/asm/
H A Dns87303.h20 #define PMC 0x06 macro
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-platform-intel-pmc13 Display global reset setting bits for PMC.
/linux-6.15/drivers/platform/mellanox/
H A DKconfig91 Say y here to enable PMC support. The PMC driver provides access

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