History log of /linux-6.15/Documentation/ABI/testing/sysfs-platform-intel-pmc (Results 1 – 3 of 3)
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# 10317dda 27-Sep-2021 Mauro Carvalho Chehab <[email protected]>

ABI: sysfs-platform-intel-pmc: add blank lines to make it valid for ReST

The ReST format requires blank lines before/after identation changes,
for it to properly detect lists.

Fixes: ee7abc105e2b (

ABI: sysfs-platform-intel-pmc: add blank lines to make it valid for ReST

The ReST format requires blank lines before/after identation changes,
for it to properly detect lists.

Fixes: ee7abc105e2b ("platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file")
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Link: https://lore.kernel.org/r/3673e1a255ad4100c933af215b60d68ba126f820.1632740376.git.mchehab+huawei@kernel.org
Signed-off-by: Hans de Goede <[email protected]>

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# 3cb1fead 27-Sep-2021 Mauro Carvalho Chehab <[email protected]>

ABI: sysfs-platform-intel-pmc: add blank lines to make it valid for ReST

The ReST format requires blank lines before/after identation changes,
for it to properly detect lists.

Fixes: ee7abc105e2b (

ABI: sysfs-platform-intel-pmc: add blank lines to make it valid for ReST

The ReST format requires blank lines before/after identation changes,
for it to properly detect lists.

Fixes: ee7abc105e2b ("platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file")
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Link: https://lore.kernel.org/r/3673e1a255ad4100c933af215b60d68ba126f820.1632740376.git.mchehab+huawei@kernel.org
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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Revision tags: v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7
# ee7abc10 11-Apr-2021 Tamar Mashiah <[email protected]>

platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file

During PCH (platform/board) manufacturing process a global platform
reset has to be induced in order for the confi

platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file

During PCH (platform/board) manufacturing process a global platform
reset has to be induced in order for the configuration changes take
the effect upon following platform reset. This is an internal platform
state and is not intended to be used in the regular platform resets.
The setting is exposed via ETR3 (Extended Test Mode Register 3).
After the manufacturing process is completed the register cannot be
written anymore and is hardware locked.
This setting was commonly done by accessing PMC registers via /dev/mem
but due to security concerns /dev/mem access is much more restricted,
hence the reason for exposing this setting via the dedicated sysfs
interface.
To prevent post manufacturing abuse the register is protected
by hardware locking and the file is set to read-only mode via is_visible
handler.

The register in MMIO space is defined for Cannon Lake and newer PCHs.

Cc: Hans de Goede <[email protected]>
Cc: David E Box <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Tamar Mashiah <[email protected]>
Signed-off-by: Tomas Winkler <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>

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