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Searched refs:PACKETJ (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c52 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
77 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); in jpeg_v1_0_decode_ring_set_patch_ring()
110 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); in jpeg_v1_0_decode_ring_set_patch_ring()
116 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); in jpeg_v1_0_decode_ring_set_patch_ring()
190 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
209 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
279 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
374 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_reg_wait()
378 PACKETJ(0, 0, 0, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_reg_wait()
410 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_wreg()
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H A Djpeg_v2_0.c468 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
486 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
534 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_fence()
538 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v2_0_dec_ring_emit_fence()
559 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
606 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
629 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
632 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_reg_wait()
662 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
665 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_wreg()
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H A Djpeg_v4_0_3.c732 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, in jpeg_v4_0_3_dec_ring_insert_start()
753 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, in jpeg_v4_0_3_dec_ring_insert_end()
798 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_emit_fence()
801 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_emit_fence()
804 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v4_0_3_dec_ring_emit_fence()
868 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_emit_ib()
897 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
900 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v4_0_3_dec_ring_emit_reg_wait()
936 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
939 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v4_0_3_dec_ring_emit_wreg()
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H A Djpeg_v2_5.c491 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_6_dec_ring_insert_start()
495 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_6_dec_ring_insert_start()
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_6_dec_ring_insert_end()
513 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_6_dec_ring_insert_end()
H A Damdgpu_jpeg.c203 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0); in amdgpu_jpeg_dec_set_reg()
206 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); in amdgpu_jpeg_dec_set_reg()
H A Dsoc15d.h74 #define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \ macro