464 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_insert_start()
468 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_insert_start()
482 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_insert_end()
486 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_insert_end()
506 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
510 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
514 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
518 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
522 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
526 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
530 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_fence()
534 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_emit_fence()
538 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));  in jpeg_v2_0_dec_ring_emit_fence()
559 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
563 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
571 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
575 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
579 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
583 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
587 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
591 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
595 	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));  in jpeg_v2_0_dec_ring_emit_ib()
598 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
602 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
606 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_ib()
616 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_reg_wait()
620 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_reg_wait()
624 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_reg_wait()
629 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));  in jpeg_v2_0_dec_ring_emit_reg_wait()
632 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_emit_reg_wait()
657 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in jpeg_v2_0_dec_ring_emit_wreg()
662 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));  in jpeg_v2_0_dec_ring_emit_wreg()
665 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in jpeg_v2_0_dec_ring_emit_wreg()
678 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));  in jpeg_v2_0_dec_ring_nop()