drm/amdgpu: update and cleanup PM4 headers

Consolidate PM4 definitions. Most of these were previously
only defined in UMDs. Add them here as well and sync with
latest packets. Also no need to inc

drm/amdgpu: update and cleanup PM4 headers

Consolidate PM4 definitions. Most of these were previously
only defined in UMDs. Add them here as well and sync with
latest packets. Also no need to include soc15d.h on gfx10+.

Reviewed-by: Feifei Xu <[email protected]>
Suggested-by: Saurabh Verma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Add PACKET3_RUN_CLEANER_SHADER for cleaner shader execution

This commit adds the PACKET3_RUN_CLEANER_SHADER definition. This packet
is a command packet used to instruct the GPU to execut

drm/amdgpu: Add PACKET3_RUN_CLEANER_SHADER for cleaner shader execution

This commit adds the PACKET3_RUN_CLEANER_SHADER definition. This packet
is a command packet used to instruct the GPU to execute the cleaner
shader.

The cleaner shader is a piece of GPU code that is used to clear or
initialize certain GPU resources, such as Local Data Share (LDS), Vector
General Purpose Registers (VGPRs), and Scalar General Purpose Registers
(SGPRs). Clearing these resources is important for ensuring data
isolation between different workloads running on the GPU.

The PACKET3_RUN_CLEANER_SHADER packet is used to trigger the execution
of the cleaner shader on the GPU. The packet consists of a header
followed by a RESERVED field, which is programmed to zero. When the GPU
receives this packet, it fetches and executes the cleaner shader
instructions from the location specified in the packet.

The cleaner shader feature helps to enhances security and reliability by
preventing data leaks between workloads.

Cc: Christian König <[email protected]>
Cc: Alex Deucher <[email protected]>
Signed-off-by: Srinivasan Shanmugam <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/amdgpu: command submission parser for JPEG

Add JPEG IB command parser to ensure registers
in the command are within the JPEG IP block.

Reviewed-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: command submission parser for JPEG

Add JPEG IB command parser to ensure registers
in the command are within the JPEG IP block.

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: David (Ming Qiang) Wu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
(cherry picked from commit a7f670d5d8e77b092404ca8a35bb0f8f89ed3117)
Cc: [email protected]

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drm/amd/amdgpu: command submission parser for JPEG

Add JPEG IB command parser to ensure registers
in the command are within the JPEG IP block.

Reviewed-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: command submission parser for JPEG

Add JPEG IB command parser to ensure registers
in the command are within the JPEG IP block.

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: David (Ming Qiang) Wu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Modify unmap_queue format for gfx9 (v6)

1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for t

drm/amdgpu: Modify unmap_queue format for gfx9 (v6)

1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.

v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer Preemption for gfx9 by default.
v5: Optimize the flag bit set for emit_fence.
v6: Modify log message for preemption timeout.

Cc: Christian Koenig <[email protected]>
Cc: Michel Dänzer <[email protected]>
Cc: Luben Tuikov <[email protected]>
Signed-off-by: Jiadong.Zhu <[email protected]>
Acked-by: Christian König <[email protected]>
Acked-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion

Add this for gfx10 and gfx9.

v2: Fix identation

Signed-off-by: Andrey Grodzovsky <[email protected]>
Reviewed-by: Luben Tuikov <luben.tu

drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion

Add this for gfx10 and gfx9.

v2: Fix identation

Signed-off-by: Andrey Grodzovsky <[email protected]>
Reviewed-by: Luben Tuikov <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add tmz bit in frame control packet

This patch adds tmz bit in frame control pm4 packet, and it will used in future.

Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deuch

drm/amdgpu: add tmz bit in frame control packet

This patch adds tmz bit in frame control pm4 packet, and it will used in future.

Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add jpeg packet defines to soc15d.h

Add new packet for vcn jpeg, including condition checks, types and packet

Signed-off-by: Boyuan Zhang <[email protected]>
Reviewed-by: Christian K

drm/amdgpu: add jpeg packet defines to soc15d.h

Add new packet for vcn jpeg, including condition checks, types and packet

Signed-off-by: Boyuan Zhang <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fences

There is a new IB flag that enables this new behavior.
Full invalidation is unnecessary for RELEASE_MEM and doesn't make s

drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fences

There is a new IB flag that enables this new behavior.
Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense
when draw calls from two adjacent gfx IBs run in parallel. This will be
the new default for Mesa.

v2: bump the version

Signed-off-by: Marek Olšák <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Add GFXv9 TLB invalidation packet definition

Signed-off-by: Shaoyun Liu <[email protected]>
Signed-off-by: Jay Cornwall <[email protected]>
Signed-off-by: Felix Kuehling <Felix.Kueh

drm/amdgpu: Add GFXv9 TLB invalidation packet definition

Signed-off-by: Shaoyun Liu <[email protected]>
Signed-off-by: Jay Cornwall <[email protected]>
Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Oded Gabbay <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>

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drm/amdgpu: fix vega10 graphic hang issue in S3 test

mmVGT_INDEX_TYPE has no default value, need to make sure
it's initialized when gfx is initialized.

Signed-off-by: Ken Wang <[email protected]>
Re

drm/amdgpu: fix vega10 graphic hang issue in S3 test

mmVGT_INDEX_TYPE has no default value, need to make sure
it's initialized when gfx is initialized.

Signed-off-by: Ken Wang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/gfx9: move define to header file

rather than defining it locally.

Reviewed-by: Junwei Zhang <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: A

drm/amdgpu/gfx9: move define to header file

rather than defining it locally.

Reviewed-by: Junwei Zhang <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu:new PM4 entry for VI/AI

TMZ package will be used for VULKAN/CHAINED-IB MCBP

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-

drm/amdgpu:new PM4 entry for VI/AI

TMZ package will be used for VULKAN/CHAINED-IB MCBP

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add KIQ packet defines to soc15d.h

Will be used in subsequent commits rather rather than
magic numbers.

Reviewed-by: monk liu <[email protected]>
Signed-off-by: Alex Deucher <alexander.d

drm/amdgpu: add KIQ packet defines to soc15d.h

Will be used in subsequent commits rather rather than
magic numbers.

Reviewed-by: monk liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu:enable mcbp for gfx9(v2)

set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.

Signed-o

drm/amdgpu:enable mcbp for gfx9(v2)

set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: init kiq and kcq for vega10

Init kiq via cpu mmio and init kcq through kiq.

Signed-off-by: Xiangliang Yu <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by:

drm/amdgpu: init kiq and kcq for vega10

Init kiq via cpu mmio and init kcq through kiq.

Signed-off-by: Xiangliang Yu <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add common soc15 headers

These are used by various IP modules.

Acked-by: Christian König <[email protected]>
Signed-off-by: Ken Wang <[email protected]>
Signed-off-by: Alex D

drm/amdgpu: add common soc15 headers

These are used by various IP modules.

Acked-by: Christian König <[email protected]>
Signed-off-by: Ken Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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