Home
last modified time | relevance | path

Searched refs:NBIO_HWIP (Results 1 – 22 of 22) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v7_2.c61 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_get_rev_id()
80 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_mc_access_enable()
264 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_update_medium_grain_light_sleep()
371 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_init_registers()
396 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_init_registers()
H A Ddimgrey_cavefish_reg_init.c39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
H A Dvega10_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
H A Damdgpu_discovery.c223 [NBIO_HWIP] = NBIF_HWID,
2594 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); in amdgpu_discovery_set_ip_blocks()
2616 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); in amdgpu_discovery_set_ip_blocks()
2639 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); in amdgpu_discovery_set_ip_blocks()
2656 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2679 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); in amdgpu_discovery_set_ip_blocks()
2709 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); in amdgpu_discovery_set_ip_blocks()
2734 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); in amdgpu_discovery_set_ip_blocks()
2838 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in amdgpu_discovery_set_ip_blocks()
H A Dnbio_v7_0.c280 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_0_init_registers()
H A Dnbio_v7_4.c345 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) && in nbio_v7_4_init_registers()
704 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4)) in nbio_v7_4_program_aspm()
H A Dnbio_v7_7.c249 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_7_init_registers()
H A Dnbio_v7_11.c277 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_11_init_registers()
H A Damdgpu_dev_coredump.c51 [NBIO_HWIP] = "NBIO",
H A Dnbio_v2_3.c535 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) != IP_VERSION(3, 3, 0)) in nbio_v2_3_clear_doorbell_interrupt()
H A Dsoc24.c544 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc24_common_set_clockgating_state()
H A Dnbio_v4_3.c340 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(4, 3, 0)) { in nbio_v4_3_init_registers()
H A Dnbio_v7_9.c49 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); in nbio_v7_9_get_rev_id()
H A Dsoc21.c959 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc21_common_set_clockgating_state()
H A Dnv.c1051 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nv_common_set_clockgating_state()
H A Dsoc15.c1419 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc15_common_set_clockgating_state()
H A Damdgpu.h715 NBIO_HWIP, enumerator
H A Damdgpu_ras.c3947 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in amdgpu_ras_init()
/linux-6.15/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c2053 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; in amdgpu_dm_init()