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/linux-6.15/Documentation/arch/powerpc/
H A Dkvm-nested.rst40 state. The L0 then starts this L2 and runs until an L2 exit condition
41 is reached. Once the L2 exits, the state of the L2 is given back to
43 and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
44 vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
140 This is called to create an L2. A unique ID of the L2 created
142 identify the L2::
162 This is called to create a vCPU associated with an L2. The L2 id
237 This is called to set L2 wide or vCPU specific L2 state. This info is
283 This is called to run an L2 vCPU. The L2 and vCPU IDs are passed in as
371 specific L2 vCPU (eg. GPR state). Only L2 VCPU state maybe be set by
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/linux-6.15/arch/mips/cavium-octeon/
H A DKconfig31 bool "Lock often used kernel code in the L2"
34 Enable locking parts of the kernel into the L2 cache.
37 bool "Lock the TLB handler in L2"
41 Lock the low level TLB fast path into L2.
44 bool "Lock the exception handler in L2"
48 Lock the low level exception handler into L2.
51 bool "Lock the interrupt handler in L2"
55 Lock the low level interrupt handler into L2.
58 bool "Lock the 2nd level interrupt handler in L2"
62 Lock the 2nd level interrupt handler in L2.
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/linux-6.15/Documentation/devicetree/bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
42 - reg : Address and size of L2 cache controller registers
43 - cache-size : Size of the entire L2 cache
44 - interrupts : Error interrupt of L2 controller
45 - cache-line-size : Size of L2 cache lines
49 L2: l2-cache-controller@20000 {
53 cache-size = <0x40000>; // L2,256K
H A Dl2c2x0.yaml7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
45 # maintenance operations on L1 are broadcasted to the L2 and L2
123 description: If present then L2 is forced to Write through mode
165 description: enable parity checking on the L2 cache (L220 or PL310).
173 description: enable ECC protection on the L2 cache
177 description: disable the outer sync operation on the L2 cache.
199 L2 dynamic clock gating. Value: <0> (forcibly
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H A Dbaikal,bt1-l2-ctl.yaml8 title: Baikal-T1 L2-cache Control Block
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
17 L2-cache controller block is responsible for the tuning. Its DT node is
/linux-6.15/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
335 ; However the context returning might not have taken L2 intr itself
337 ; Special considerations needed for the context which took L2 intr
339 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
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/linux-6.15/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
/linux-6.15/Documentation/virt/kvm/x86/
H A Drunning-nested-guests.rst14 | L2 | | L2 |
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
139 .. note:: If you suspect your L2 (i.e. nested guest) is running slower,
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
205 - Migrating a nested guest (L2) to another L1 guest on the *same* bare
208 - Migrating a nested guest (L2) to another L1 guest on a *different*
211 - Migrating a nested guest (L2) to a bare metal host.
217 L0, L1 and L2; this can result in tedious back-n-forth between the bug
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/linux-6.15/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-dt.txt33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
/linux-6.15/security/apparmor/include/
H A Dperms.h186 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
189 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
193 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
194 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
196 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
197 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
/linux-6.15/Documentation/devicetree/bindings/arm/calxeda/
H A Dl2ecc.yaml7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
/linux-6.15/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts44 next-level-cache = <&L2>;
51 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
166 L2: cache-controller@1e00a000 { label
227 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
272 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
286 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
H A Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
H A Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
/linux-6.15/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml35 next-level-cache = <&L2>;
46 next-level-cache = <&L2>;
92 next-level-cache = <&L2>;
103 next-level-cache = <&L2>;
114 next-level-cache = <&L2>;
125 next-level-cache = <&L2>;
176 next-level-cache = <&L2>;
187 next-level-cache = <&L2>;
198 next-level-cache = <&L2>;
209 next-level-cache = <&L2>;
/linux-6.15/Documentation/locking/
H A Dlockdep-design.rst145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
612 L1 -> L2
613 L2 -> L3
621 the L2 in L2 -> L3, and so on. After this, all of the Lx in Lx -> Lx+1 are
624 And then because we have L1 -> L2, so the holder of L1 is going to acquire L2
625 in L1 -> L2, however since L2 is already held by another CPU/task, plus L1 ->
627 means either L2 in L1 -> L2 is a non-recursive locker (blocked by anyone) or
628 the L2 in L2 -> L3, is writer (blocking anyone), therefore the holder of L1
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/linux-6.15/arch/arm/boot/dts/nxp/vf/
H A Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
/linux-6.15/Documentation/translations/it_IT/locking/
H A Dlockdep-design.rst143 <L1> -> <L2>
144 <L2> -> <L1>
531 L1 -> L2
619 L1 -> L2 ... -> Ln -> L1
623 L1 -> L2
624 L2 -> L3
633 un altro prende L2 in L2 -> L3, e così via. Alla fine, tutti i Lx in Lx -> Lx+1
636 Poi visto che abbiamo L1 -> L2, chi trattiene L1 vorrà acquisire L2 in L1 -> L2,
638 L2 è già trattenuto da un altro processo/processore, ed in più L1 -> L2 e L2 ->
640 in L1 -> L2 non è un bloccatore non ricorsivo (bloccabile da chiunque), e L2 in
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/linux-6.15/arch/powerpc/perf/
H A Disa207-common.c226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/linux-6.15/arch/powerpc/boot/dts/fsl/
H A Dmpc8572ds_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
58 cache-size = <0x80000>; // L2, 512K
80 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
/linux-6.15/Documentation/networking/
H A Dipvlan.rst14 the master device share the L2 with its slave devices. I have developed this
45 (b) This command will create IPvlan link in L2 bridge mode::
49 (c) This command will create an IPvlan device in L2 private mode::
53 (d) This command will create an IPvlan device in L2 vepa mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
68 4.1 L2 mode:
81 master device for the L2 processing and routing from that instance will be
133 namespace where L2 on the slave could be changed / misused.
/linux-6.15/drivers/net/ethernet/intel/libie/
H A Drx.c36 LIBIE_RX_PT(L2, NOT_FRAG, NONE, NONE, NOT_FRAG, iprot, pl)
37 #define LIBIE_RX_PT_L2 __LIBIE_RX_PT_L2(NONE, L2)
38 #define LIBIE_RX_PT_TS __LIBIE_RX_PT_L2(TIMESYNC, L2)
/linux-6.15/arch/alpha/kernel/
H A Dsetup.c1196 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1219 L2 = external_cache_probe(128*1024, 5); in determine_cpu_caches()
1233 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); in determine_cpu_caches()
1247 L2 = CSHAPE (96*1024, width, 3); in determine_cpu_caches()
1281 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); in determine_cpu_caches()
1283 L2 = external_cache_probe(512*1024, 6); in determine_cpu_caches()
1295 L2 = external_cache_probe(1024*1024, 6); in determine_cpu_caches()
1302 L2 = CSHAPE(7*1024*1024/4, 6, 7); in determine_cpu_caches()
1308 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1314 alpha_l2_cacheshape = L2; in determine_cpu_caches()
/linux-6.15/drivers/cache/
H A DKconfig5 bool "Andes Technology AX45MP L2 Cache controller"
9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
/linux-6.15/arch/arm/boot/dts/broadcom/
H A Dbcm4708.dtsi31 next-level-cache = <&L2>;
38 next-level-cache = <&L2>;

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