ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

THe high level structure of most ARC exception handlers is
1. save regfile with EXCEPTION_PROLOGUE
2. setup r0: EFA (not part of pt_regs)

ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

THe high level structure of most ARC exception handlers is
1. save regfile with EXCEPTION_PROLOGUE
2. setup r0: EFA (not part of pt_regs)
3. setup r1: pointer to pt_regs (SP)
4. drop down to pure kernel mode (from exception)
5. call the Linux "C" handler

Remove the boiler plate code by moving #2, #3, #4 into #1.

The exceptions to most exceptions are syscall Trap and Machine check
which don't do some of above for various reasons, so call a newly
introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original
EXCEPTION_PROLOGUE)

Tested-by: Pavel Kozlov <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry: ARcompact EV_ProtV to use r10 directly

Signed-off-by: Vineet Gupta <[email protected]>

ARC: entry: EV_Trap expects r10 (vs. r9) to have exception cause

avoids 1 MOV instruction in light of double load/store code

Signed-off-by: Vineet Gupta <[email protected]>

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Enrico Weigelt <[email protected]>
Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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ARC: typos fix in kernel/entry-compact.S

Signed-off-by: Liav Rehana <[email protected]>
Signed-off-by: Noam Camus <[email protected]>
Reviewed-by: Alexey Brodkin <[email protected]>
Signed-of

ARC: typos fix in kernel/entry-compact.S

Signed-off-by: Liav Rehana <[email protected]>
Signed-off-by: Noam Camus <[email protected]>
Reviewed-by: Alexey Brodkin <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: ARCompact entry: elide re-reading ECR in ProtV handler

Signed-off-by: Vineet Gupta <[email protected]>

ARC: [intc-compact] simplify code for 2 priority levels

ARC700 support for 2 interrupt priorities historically allowed even slow
perpherals such as emac and uart to setup high priority interrupts
wh

ARC: [intc-compact] simplify code for 2 priority levels

ARC700 support for 2 interrupt priorities historically allowed even slow
perpherals such as emac and uart to setup high priority interrupts
which was wrong from the beginning as they could possibly delay the more
critical timer interrupt.

The hardware support for 2 level interrupts in ARCompact is less than
ideal anyways (judging from the "hacks" in low level entry code and thus
is not used in productions systems I know of.

So reduce the scope of this to timer only, thereby reducing a bunch of
complexity.

Signed-off-by: Vineet Gupta <[email protected]>

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ARCv2: Enable LOCKDEP

- The asm helpers for calling into irq tracer were missing

- Add calls to above helpers in low level assembly entry code for ARCv2

- irq_save() uses CLRI to disable interrupt

ARCv2: Enable LOCKDEP

- The asm helpers for calling into irq tracer were missing

- Add calls to above helpers in low level assembly entry code for ARCv2

- irq_save() uses CLRI to disable interrupts and returns the prev interrupt
state (in STATUS32) in a specific encoding (and not the raw value of
STATUS32). This is usable with SETI in irq_restore(). However
save_flags() reads the raw value of STATUS32 which doesn't pair with
irq_save/restore() and thus needs fixing.

Signed-off-by: Evgeny Voevodin <[email protected]>
[vgupta: updated changelog and also added some comments]
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [arcompact] Handle bus error from userspace as Interrupt not exception

Bus errors from userspace on ARCompact based cores are handled by core
as a high priority L2 interrupt but current code tr

ARC: [arcompact] Handle bus error from userspace as Interrupt not exception

Bus errors from userspace on ARCompact based cores are handled by core
as a high priority L2 interrupt but current code treated it as interrupt
Handling an interrupt like exception is certainly not going to go unnoticed.
(and it worked so far as we never saw a Bus error from userspace until
IPPK guys tested a DDR controller with ECC error detection etc hence
needed to explicitly trigger/handle such errors)

- So move mem_service exception handler from common code into ARCv2 code.
- In ARCompact code, define mem_service as L2 interrupt handler which
just drops down to pure kernel mode and goes of to enqueue SIGBUS

Reported-by: Nelson Pereira <[email protected]>
Tested-by: Ana Martins <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes

For Run-on-reset, non masters need to spin wait. For Halt-on-reset they
can jump to entry point directly.

Also while at it, made

ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes

For Run-on-reset, non masters need to spin wait. For Halt-on-reset they
can jump to entry point directly.

Also while at it, made reset vector handler as "the" entry point for
kernel including host debugger based boot (which uses the ELF header
entry point)

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [arcompact] entry.S: Elide extra check/branch in exception ret path

This is done by improving the laddering logic !

Before:

if Exception
goto excep_or_pure_k_ret

if !Interrupt(L2

ARC: [arcompact] entry.S: Elide extra check/branch in exception ret path

This is done by improving the laddering logic !

Before:

if Exception
goto excep_or_pure_k_ret

if !Interrupt(L2)
goto l1_chk
else
INTERRUPT_EPILOGUE 2

l1_chk:
if !Interrupt(L1) (i.e. pure kernel mode)
goto excep_or_pure_k_ret
else
INTERRUPT_EPILOGUE 1

excep_or_pure_k_ret:
EXCEPTION_EPILOGUE

Now:

if !Interrupt(L1 or L2) (i.e. exception or pure kernel mode)
goto excep_or_pure_k_ret

; guaranteed to be an interrupt
if !Interrupt(L2)
goto l1_ret
else
INTERRUPT_EPILOGUE 2

; by virtue of above, no need to chk for L1 active
l1_ret:
INTERRUPT_EPILOGUE 1

excep_or_pure_k_ret:
EXCEPTION_EPILOGUE

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [arcompact] entry.S: Document preemption games for L2 intr

Signed-off-by: Vineet Gupta <[email protected]>

ARC: entry.S: use single EXCEPTION_PROLOGUE

Returning from pure kernel mode and exception mode use the same code
anyways. Remove one the duplicate blocks

Signed-off-by: Vineet Gupta <vgupta@synopsy

ARC: entry.S: use single EXCEPTION_PROLOGUE

Returning from pure kernel mode and exception mode use the same code
anyways. Remove one the duplicate blocks

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry.S: move some code around for cache locality in return path

Signed-off-by: Vineet Gupta <[email protected]>

ARC: entry.S: split into ARCompact ISA specific, common bits

Signed-off-by: Vineet Gupta <[email protected]>