Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 48) sorted by relevance
12
695 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()726 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()783 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()809 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
246 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()304 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
43 AMDGPU_IRQ_STATE_ENABLE, enumerator
288 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()352 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
507 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()540 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
464 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()509 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
590 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()606 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
3059 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()3106 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_reg_fault_state()3110 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_reg_fault_state()3120 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_priv_reg_fault_state()3146 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_bad_op_fault_state()3150 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_bad_op_fault_state()3160 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_bad_op_fault_state()3185 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_inst_fault_state()3189 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_inst_fault_state()
491 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbif_v6_3_1_set_ras_err_event_athub_irq_state()
555 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
323 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in vpe_v6_1_set_trap_irq_state()
538 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
999 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()1015 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
4654 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_gfx_eop_interrupt_state()4705 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_compute_eop_interrupt_state()4813 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_reg_fault_state()4822 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()4836 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()4859 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_bad_op_fault_state()4868 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()4882 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()4904 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_inst_fault_state()4913 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_inst_fault_state()
1110 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()1126 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
5958 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()5961 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()6010 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()6056 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()6059 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()6069 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()6092 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_bad_op_fault_state()6095 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_bad_op_fault_state()6125 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()6128 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()[all …]
573 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbio_v4_3_set_ras_err_event_athub_irq_state()
1337 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()1353 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
6195 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()6252 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_compute_eop_interrupt_state()6360 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_reg_fault_state()6369 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()6383 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()6406 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_bad_op_fault_state()6415 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()6429 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()6451 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_inst_fault_state()6460 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
70 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v12_0_vm_fault_interrupt_state()
80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v11_0_vm_fault_interrupt_state()
3215 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3244 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3278 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()3303 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
1054 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
733 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()