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Searched refs:AMDGPU_GPU_PAGE_ALIGN (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.c200 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_vcn_sw_init()
203 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); in amdgpu_vcn_sw_init()
206 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); in amdgpu_vcn_sw_init()
209 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
594 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_send_msg()
653 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_create_msg()
688 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_destroy_msg()
773 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_sw_send_msg()
918 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_create_msg()
985 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_destroy_msg()
H A Damdgpu_gart.h38 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) macro
H A Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
H A Dvcn_v5_0_1.c321 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_1_mc_resume()
366 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); in vcn_v5_0_1_mc_resume()
386 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_1_mc_resume_dpg_mode()
476 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
H A Dvcn_v4_0_3.c449 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_3_mc_resume()
506 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_mc_resume()
526 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_3_mc_resume_dpg_mode()
616 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1020 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v4_0_3_start_sriov()
1097 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c383 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_0_mc_resume()
426 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); in vcn_v5_0_0_mc_resume()
446 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_0_mc_resume_dpg_mode()
532 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0.c466 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume()
509 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_mc_resume()
528 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume_dpg_mode()
614 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1385 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v4_0_start_sriov()
1484 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_start_sriov()
H A Dvcn_v4_0_5.c405 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_5_mc_resume()
448 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_5_mc_resume()
468 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_5_mc_resume_dpg_mode()
559 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v2_0.c379 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v2_0_mc_resume()
428 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_0_mc_resume()
437 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
524 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1941 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v2_0_start_sriov()
H A Dvcn_v3_0.c521 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4); in vcn_v3_0_mc_resume()
566 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v3_0_mc_resume()
574 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
661 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1416 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v3_0_start_sriov()
H A Dvcn_v2_5.c617 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v2_5_mc_resume()
660 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_5_mc_resume()
668 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
755 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1435 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); in vcn_v2_5_sriov_start()
H A Damdgpu_vm_pt.c124 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_pt_num_entries(adev, level) * 8); in amdgpu_vm_pt_size()
H A Damdgpu_vce.c466 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); in amdgpu_vce_get_create_msg()
H A Dvcn_v1_0.c351 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v1_0_mc_resume_spg_mode()
419 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); in vcn_v1_0_mc_resume_dpg_mode()
H A Damdgpu_uvd.c320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_uvd_sw_init()
H A Duvd_v7_0.c820 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v7_0_sriov_start()