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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td322 $ptr), sub1)>;
439 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),
440 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),
441 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)
458 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),
459 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),
460 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)
480 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))), sub1)
489 $src1), sub1)
794 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1)),
[all …]
H A DSIInstructions.td1987 sub1)
1997 sub1)
2007 sub1)
2063 sub1)
2073 sub1)
2083 sub1)
2324 (i32 (EXTRACT_SUBREG VReg_64:$z, sub1))), sub1)
2345 (i32 (EXTRACT_SUBREG VReg_64:$z, sub1))), sub1)
2892 sub1)
2917 sub1)
[all …]
H A DSIRegisterInfo.td44 list<SubRegIndex> ret2 = [sub0, sub1];
45 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
46 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
199 let SubRegIndices = [sub0, sub1];
208 let SubRegIndices = [sub0, sub1];
238 let SubRegIndices = [sub0, sub1];
262 let SubRegIndices = [sub0, sub1];
291 let SubRegIndices = [sub0, sub1];
301 let SubRegIndices = [sub0, sub1];
310 let SubRegIndices = [sub0, sub1];
[all …]
H A DR600RegisterInfo.cpp26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
H A DGCNPreRAOptimizations.cpp164 case AMDGPU::sub1: in processReg()
H A DSIInstrInfo.cpp2653 .addImm(AMDGPU::sub1); in expandMovDPP64()
3385 case AMDGPU::sub1: in FoldImmediate()
5560 if (SubIdx == AMDGPU::sub1) in buildExtractSubRegOrImm()
6722 .addImm(AMDGPU::sub1); in legalizeOperands()
7697 .addImm(AMDGPU::sub1); in splitScalar64BitUnaryOp()
7803 .addImm(AMDGPU::sub1); in splitScalarSMulU64()
7872 .addImm(AMDGPU::sub1); in splitScalarSMulPseudo()
7941 .addImm(AMDGPU::sub1); in splitScalar64BitBinaryOp()
8068 .addImm(AMDGPU::sub1); in splitScalar64BitBFE()
8087 .addImm(AMDGPU::sub1); in splitScalar64BitBFE()
[all …]
H A DAMDGPUInstructionSelector.cpp278 case AMDGPU::sub1: in getSubOperand64()
410 .addImm(AMDGPU::sub1); in selectG_ADD_SUB()
1443 .addImm(AMDGPU::sub1); in selectBallot()
2429 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2493 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2649 .addImm(AMDGPU::sub1); in selectG_CONSTANT()
2713 .addImm(AMDGPU::sub1); in selectG_FNEG()
2755 .addImm(AMDGPU::sub1); in selectG_FABS()
3056 .addImm(AMDGPU::sub1); in selectG_PTRMASK()
3293 .addImm(AMDGPU::sub1); in selectBufferLoadLds()
[all …]
H A DR600Instructions.td1738 def : Extract_Element <f32, v4f32, 1, sub1>;
1743 def : Insert_Element <f32, v4f32, 1, sub1>;
1748 def : Extract_Element <i32, v4i32, 1, sub1>;
1753 def : Insert_Element <i32, v4i32, 1, sub1>;
1758 def : Extract_Element <f32, v2f32, 1, sub1>;
1761 def : Insert_Element <f32, v2f32, 1, sub1>;
1764 def : Extract_Element <i32, v2i32, 1, sub1>;
1767 def : Insert_Element <i32, v2i32, 1, sub1>;
H A DSIFrameLowering.cpp185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
427 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
466 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
814 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup()
851 Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup()
1680 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub1)); in determineCalleeSavesSGPR()
H A DVOP2Instructions.td859 (i32 (EXTRACT_SUBREG $src0, sub1)),
860 (i32 (EXTRACT_SUBREG $src1, sub1))
861 ), sub1
874 (InstHi $src0, $src1), sub1)
1028 (i32 (EXTRACT_SUBREG $src0, sub1)),
1029 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)
1038 (i32 (EXTRACT_SUBREG $src0, sub1)),
1039 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)
1134 (V_MOV_B32_e32 (i32 0)), sub1)
H A DR600MachineScheduler.cpp255 case R600::sub1: in getAluKind()
H A DVOP3Instructions.td400 ), VGPR_32)), sub1)
713 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)),
714 (i32 (EXTRACT_SUBREG $src1, sub1)),
715 (i32 (EXTRACT_SUBREG $src2, sub1))), sub1)>;
737 (i32 (IMPLICIT_DEF)), sub1),
H A DAMDGPUISelDAGToDAG.cpp429 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in buildSMovImm64()
574 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
831 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64()
1036 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32); in SelectMUL_LOHI()
1673 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffsetImpl()
2063 CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32), in Expand32BitAddress()
2988 Undef, CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32) }; in SelectVOP3PMods()
H A DBUFInstructions.td1369 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1465 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1673 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1774 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1826 defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3);
1870 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
2168 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
2241 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
H A DSILoadStoreOptimizer.cpp1210 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; in mergeRead2Pair()
1846 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs()
2012 .addImm(AMDGPU::sub1); in computeBase()
H A DSIISelLowering.cpp4791 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
4838 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
4870 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
5012 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
5067 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5098 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
14494 case AMDGPU::sub1: return 1; in SubIdx2Lane()
14660 case AMDGPU::sub0: Idx = AMDGPU::sub1; break; in adjustWritemask()
14661 case AMDGPU::sub1: Idx = AMDGPU::sub2; break; in adjustWritemask()
14981 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32) in wrapAddr64Rsrc()
[all …]
H A DSMInstructions.td1058 (S_MOV_B32 (i32 0)), sub1)> {
1086 (i64 (REG_SEQUENCE SReg_64, $sbase, sub0, (i32 (S_MOV_B32 (i32 0))), sub1)),
H A DSOPInstructions.td1767 (S_MOV_B32 (i32 0)), sub1))
1890 (S_MOV_B32 (i32 0)), sub1)
1896 … (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1)
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmarvell-8xxx.txt28 "marvell,caldata-txpwrlimit-5g-sub1" (length = 688).
/freebsd-14.2/contrib/file/magic/Magdir/
H A Dicc71 # Profile version major.4bit-minor.sub1.sub2 like 4.3.0.0 (04300000h)
/freebsd-14.2/usr.bin/vgrind/
H A Dvgrindefs.src94 stjoin sub1 t times tnull tokno ttype:
/freebsd-14.2/contrib/googletest/googlemock/test/
H A Dgmock-matchers-comparisons_test.cc2221 AmbiguousCastTypes::DerivedSub1 sub1; in TEST() local
2235 as_base_ptr = &sub1; in TEST()
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Drk3288-veyron-jerry.dts121 marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td293 defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;

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