Lines Matching refs:sub1
4772 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
4777 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
4791 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
4838 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
4846 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
4848 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
4870 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
4928 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
5012 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
5067 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5075 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
5077 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
5098 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
14494 case AMDGPU::sub1: return 1; in SubIdx2Lane()
14660 case AMDGPU::sub0: Idx = AMDGPU::sub1; break; in adjustWritemask()
14661 case AMDGPU::sub1: Idx = AMDGPU::sub2; break; in adjustWritemask()
14981 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32) in wrapAddr64Rsrc()
15007 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); in buildRSRC()
15023 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32), in buildRSRC()