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Searched refs:hasSubClassEq (Results 1 – 25 of 45) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp47 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
51 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
52 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
55 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
58 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetMachine.cpp282 return RISCV::VRRegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
283 RISCV::VRM2RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
284 RISCV::VRM4RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
285 RISCV::VRM8RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
286 RISCV::VRN2M1RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
287 RISCV::VRN2M2RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
288 RISCV::VRN2M4RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
289 RISCV::VRN3M1RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
290 RISCV::VRN3M2RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
291 RISCV::VRN4M1RegClass.hasSubClassEq(&RC) || in onlyAllocateRVVReg()
[all …]
H A DRISCVRVVInitUndef.cpp98 if (RISCV::VRM8RegClass.hasSubClassEq(RC)) in getVRLargestSuperClass()
100 if (RISCV::VRM4RegClass.hasSubClassEq(RC)) in getVRLargestSuperClass()
102 if (RISCV::VRM2RegClass.hasSubClassEq(RC)) in getVRLargestSuperClass()
104 if (RISCV::VRRegClass.hasSubClassEq(RC)) in getVRLargestSuperClass()
111 return RISCV::VRRegClass.hasSubClassEq(RC) || in isVectorRegClass()
112 RISCV::VRM2RegClass.hasSubClassEq(RC) || in isVectorRegClass()
113 RISCV::VRM4RegClass.hasSubClassEq(RC) || in isVectorRegClass()
114 RISCV::VRM8RegClass.hasSubClassEq(RC); in isVectorRegClass()
H A DRISCVInstrInfo.cpp607 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
623 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
633 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
635 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
637 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
639 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
641 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
643 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
645 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
647 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp224 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
253 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
255 else if (Mips::LO64RegClass.hasSubClassEq(RC)) in storeRegToStack()
257 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in storeRegToStack()
259 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in storeRegToStack()
261 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) in storeRegToStack()
268 if (Mips::HI32RegClass.hasSubClassEq(RC)) { in storeRegToStack()
302 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
331 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
333 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
[all …]
H A DMips16InstrInfo.cpp116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp118 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
122 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
124 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
126 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
128 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
130 else if (LoongArch::CFRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
156 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
160 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
162 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
164 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp407 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
409 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
412 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
414 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
416 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
418 else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
451 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
453 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
458 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
460 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrInfo.cpp4015 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
4016 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
4017 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
4268 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4274 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4276 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4283 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4299 X86::FR16XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4303 if (X86::GR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4305 if (X86::FR64XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp736 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
737 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
4784 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
4788 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
4860 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
4884 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
4967 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
4971 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
5040 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
5064 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp39 if (!RC.hasSubClassEq(&SubRC)) in verify()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1534 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1535 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1536 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1537 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1568 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1849 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1850 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1852 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1855 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1925 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
[all …]
H A DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp555 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
558 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
594 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
597 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h125 return RC != this && hasSubClassEq(RC); in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
142 return RC->hasSubClassEq(this); in hasSuperClassEq()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp706 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
708 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
713 assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
716 assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp309 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
337 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp178 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
188 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
222 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
231 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
H A DARMBaseInstrInfo.cpp1131 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1142 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1167 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1247 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
1248 ARM::MQQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
1389 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1399 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1421 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1500 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in loadRegFromStackSlot()
1501 ARM::MQQPRRegClass.hasSubClassEq(RC) || in loadRegFromStackSlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp497 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
511 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
556 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
568 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp972 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
980 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
984 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
988 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
992 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
996 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1019 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1028 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1031 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1034 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp317 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()

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