1131       if (ARM::HPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1142       if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1149       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1156       } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1167       if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1174       } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1195       if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {  in storeRegToStackSlot()
1211       } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
1223       if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1247       if (ARM::QQPRRegClass.hasSubClassEq(RC) ||  in storeRegToStackSlot()
1248           ARM::MQQPRRegClass.hasSubClassEq(RC) ||  in storeRegToStackSlot()
1249           ARM::DQuadRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1280       if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
1286       } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1389     if (ARM::HPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1399     if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1405     } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1411     } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1421     if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1427     } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1453     if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {  in loadRegFromStackSlot()
1466     } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
1477     if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1500      if (ARM::QQPRRegClass.hasSubClassEq(RC) ||  in loadRegFromStackSlot()
1501          ARM::MQQPRRegClass.hasSubClassEq(RC) ||  in loadRegFromStackSlot()
1502          ARM::DQuadRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1530     if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
1535     } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()