638   bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));  in canFoldIntoCSel()
722   if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||  in canInsertSelect()
723       AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in canInsertSelect()
736   if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||  in canInsertSelect()
737       AArch64::FPR32RegClass.hasSubClassEq(RC)) {  in canInsertSelect()
1263     } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&  in UpdateOperandRegClass()
4784     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
4788     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
4790     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4795     } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4811     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4817     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
4819     else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4825     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4831     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4833     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4841     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
4843     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4847     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4852     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4860     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4867     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4871     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4875     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||  in storeRegToStackSlot()
4876                AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4884     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4888     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4896     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4900     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||  in storeRegToStackSlot()
4901                AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
4967     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
4971     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
4973     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4978     } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4991     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4997     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
4999     else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5005     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5011     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5013     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5021     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
5023     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5027     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5032     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5040     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5047     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5051     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5055     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||  in loadRegFromStackSlot()
5056                AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5064     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5068     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5076     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
5080     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||  in loadRegFromStackSlot()
5081                AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
6674   if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in genFNegatedMAD()
6676   else if (AArch64::FPR64RegClass.hasSubClassEq(RC))  in genFNegatedMAD()
9482             return AArch64::ZPRRegClass.hasSubClassEq(RC) ||  in isReallyTriviallyReMaterializable()
9483                    AArch64::PPRRegClass.hasSubClassEq(RC);  in isReallyTriviallyReMaterializable()