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Searched refs:getRegClassFor (Results 1 – 25 of 38) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
328 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
339 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
H A DInstrEmitter.cpp107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
212 const TargetRegisterClass *VTRC = TLI->getRegClassFor( in CreateVirtualRegisters()
275 const TargetRegisterClass *RC = TLI->getRegClassFor( in getVR()
392 ? TLI->getRegClassFor(OpVT, in AddOperand()
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
571 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
H A DFastISel.cpp321 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
793 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1528 const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty); in selectFreeze()
2190 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
H A DFunctionLoweringInfo.cpp365 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); in CreateReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg()
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt()
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock()
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs()
H A DCallingConvLower.cpp253 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp394 Register MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
404 Register MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
430 Register DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
442 Register DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
502 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
606 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
657 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
966 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
978 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
[all …]
H A DARMISelLowering.h581 getRegClassFor(MVT VT, bool isDivergent = false) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp464 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in X86FastEmitLoad()
2033 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2193 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2336 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2363 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2433 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); in X86SelectIntToFP()
2821 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerIntrinsicCall()
2903 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3163 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerArguments()
3769 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in X86MaterializeInt()
[all …]
H A DX86ISelLoweringCall.cpp1650 TargLowering.getRegClassFor(FR.VT)); in forwardMustTailParameters()
1842 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1646 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1665 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1668 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1913 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1916 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2544 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3692 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
4100 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
4112 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); in parseRegForInlineAsmConstraint()
4387 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
[all …]
H A DMipsSEISelDAGToDAG.cpp1293 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); in trySelect()
1362 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in trySelect()
H A DMipsFastISel.cpp1291 Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp407 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
420 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
438 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
574 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg); in fastMaterializeFloatZero()
2892 Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg); in selectIntToFP()
3600 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3759 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp514 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerCCCArguments()
1073 Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h545 const TargetRegisterClass *getRegClassFor(MVT VT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp712 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); in EmitSubregExt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1520 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1525 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp999 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
1036 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT)); in LowerFormalArguments()
3401 auto *ARClass = getRegClassFor(SPTy); in LowerDYNAMIC_STACKALLOC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp1253 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp712 getRegClassFor(MVT::i16)); in LowerCCCArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp649 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2909 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp842 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
1188 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp630 getRegClassFor(GRLenVT)); in lowerRETURNADDR()
3754 const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT()); in unpackFromRegLoc()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h980 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {

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