Lines Matching refs:getRegClassFor

1646   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitSignExtendToI32InReg()
1665   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicBinaryPartword()
1668     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicBinaryPartword()
1861   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));  in emitAtomicCmpSwap()
1913   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicCmpSwapPartword()
1916     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicCmpSwapPartword()
2544   Register Reg = MF.addLiveIn(RA, getRegClassFor(VT));  in lowerRETURNADDR()
3692       const TargetRegisterClass *RC = getRegClassFor(RegVT);  in LowerFormalArguments()
3762             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));  in LowerFormalArguments()
4100     RC = getRegClassFor(VT);  in parseRegForInlineAsmConstraint()
4109     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);  in parseRegForInlineAsmConstraint()
4112     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);  in parseRegForInlineAsmConstraint()
4387   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in copyByValRegs()
4506   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in writeVarArgRegs()