Home
last modified time | relevance | path

Searched refs:getOperand (Results 1 – 25 of 1083) sorted by relevance

12345678910>>...44

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp662 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
678 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
694 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
708 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
726 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
820 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
838 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
1240 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments()
1241 MI->getOperand(3).isImm()) in EmitAnyX86InstComments()
1250 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
78 .addOperand(MI.getOperand(0)) in expandJBTF()
103 .addOperand(MI.getOperand(0)) in expandNEG()
109 .addOperand(MI.getOperand(0)) in expandNEG()
110 .addOperand(MI.getOperand(0)) in expandNEG()
125 .addOperand(MI.getOperand(0)) in expandRSUBI()
131 .addOperand(MI.getOperand(0)) in expandRSUBI()
224 auto V = 1 << MI.getOperand(1).getImm(); in encodeInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp231 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
237 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
582 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0) in simplifyCode()
748 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
960 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
1032 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
1074 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) in simplifyCode()
1255 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in simplifyCode()
1687 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { in eliminateRedundantCompare()
1852 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); in eliminateRedundantCompare()
[all …]
H A DPPCVSXFMAMutate.cpp190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
252 MI.getOperand(3).setSubReg(AddSubReg); in processBlock()
255 MI.getOperand(3).setIsKill(AddRegKill); in processBlock()
258 MI.getOperand(3).setIsUndef(AddRegUndef); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
266 MI.getOperand(2).setSubReg(AddSubReg); in processBlock()
267 MI.getOperand(2).setIsKill(AddRegKill); in processBlock()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
145 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
153 if (LatrCFAlu.getOperand(Mode0Idx).getImm()) { in mergeIfPossible()
154 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
156 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
158 RootCFAlu.getOperand(KBank0LineIdx) in mergeIfPossible()
162 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
164 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
84 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
87 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
101 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
122 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
128 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
153 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandRRM()
159 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandRRM()
184 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandHM()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetStreamer.h33 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
34 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
37 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
38 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
39 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
40 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
41 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
42 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
43 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
44 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
H A DSystemZAsmPrinter.cpp43 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
69 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
70 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
72 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
73 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
74 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
123 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
124 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
133 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
134 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp178 MIBHI->getOperand(4).setIsKill(); in expandArith()
203 MIBLO->getOperand(3).setIsDead(); in expandLogic()
346 MIBHI->getOperand(4).setIsKill(); in expand()
379 MIBLO->getOperand(4).setIsKill(); in expand()
391 MIBHI->getOperand(4).setIsKill(); in expand()
1038 auto Op1 = MI.getOperand(0); in expandAtomicBinaryOp()
1039 auto Op2 = MI.getOperand(1); in expandAtomicBinaryOp()
2233 ->getOperand(3) in expandLSLB7Rd()
2284 ->getOperand(4) in expandLSRB7Rd()
2335 ->getOperand(2) in expandASRB6Rd()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
159 if (MI->getOperand(OpNum).isImm()) { in printImm8_AsmOperand()
171 if (MI->getOperand(OpNum).isImm()) { in printImm8_sh8_AsmOperand()
183 if (MI->getOperand(OpNum).isImm()) { in printImm12_AsmOperand()
194 if (MI->getOperand(OpNum).isImm()) { in printImm12m_AsmOperand()
205 if (MI->getOperand(OpNum).isImm()) { in printUimm4_AsmOperand()
215 if (MI->getOperand(OpNum).isImm()) { in printUimm5_AsmOperand()
225 if (MI->getOperand(OpNum).isImm()) { in printShimm1_31_AsmOperand()
236 if (MI->getOperand(OpNum).isImm()) { in printImm1_16_AsmOperand()
247 if (MI->getOperand(OpNum).isImm()) { in printOffset8m8_AsmOperand()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp171 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
186 N->getOperand(2), N->getOperand(3) }; in Select()
192 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
193 N->getOperand(2), N->getOperand(3) }; in Select()
199 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
200 N->getOperand(2), N->getOperand(3) }; in Select()
206 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in Select()
249 SDValue Chain = N->getOperand(0); in tryBRIND()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp97 const MCOperand &Dst = MI->getOperand(0); in printInst()
98 const MCOperand &MO1 = MI->getOperand(1); in printInst()
99 const MCOperand &MO2 = MI->getOperand(2); in printInst()
100 const MCOperand &MO3 = MI->getOperand(3); in printInst()
120 const MCOperand &Dst = MI->getOperand(0); in printInst()
163 MI->getOperand(3).getImm() == -4) { in printInst()
192 MI->getOperand(4).getImm() == 4) { in printInst()
287 switch (MI->getOperand(0).getImm()) { in printInst()
1011 if (MI->getOperand(OpNum).getReg()) { in printSBitModifierOperand()
1021 O << MI->getOperand(OpNum).getImm(); in printNoHashImmediate()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp211 Rt = L.getOperand(0); in getCompoundInsn()
222 Rt = L.getOperand(0); in getCompoundInsn()
223 Rs = L.getOperand(1); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
237 Rt = L.getOperand(2); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
250 Rt = L.getOperand(2); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
263 Rt = L.getOperand(2); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
[all …]
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp44 return Align(MI->getOperand(2).getImm()); in computeKnownAlignment()
47 int FrameIdx = MI->getOperand(1).getIndex(); in computeKnownAlignment()
62 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
332 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(), in computeKnownBitsImpl()
463 SrcBitWidth = MI.getOperand(2).getImm(); in computeKnownBitsImpl()
581 if (MI.getOperand(1).getReg() == R) { in computeKnownBitsImpl()
639 MachineOperand &Src = MI.getOperand(1); in computeNumSignBits()
649 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
657 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
681 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
[all …]
H A DCombinerHelper.cpp868 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
1368 matchEqualDefs(MI.getOperand(2), UseMI.getOperand(2)) && in matchCombineDivRem()
1369 matchEqualDefs(MI.getOperand(1), UseMI.getOperand(1))) { in matchCombineDivRem()
1411 { FirstInst->getOperand(1), FirstInst->getOperand(2) }); in applyCombineDivRem()
2820 {MI.getOperand(1), MI.getOperand(2), NewConstInstr.getReg(0)}); in applyFunnelShiftConstantModulo()
2828 return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) && in matchSelectSameVal()
2829 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(), in matchSelectSameVal()
2834 return matchEqualDefs(MI.getOperand(1), MI.getOperand(2)) && in matchBinOpSameVal()
3398 MI.getOperand(1).setReg(Not->getOperand(0).getReg()); in applyXorOfAndWithSameReg()
4591 MI.getOperand(2).setReg(RHS->getOperand(2).getReg()); in matchReassocConstantInnerRHS()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp52 MI.getOperand(3).getMetadata()->getOperand(0)) in addConstantsToTrack()
85 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
107 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics()
131 assert(MI.getOperand(2).isReg()); in insertBitcasts()
135 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
173 if (MI->getOperand(0).isReg()) { in propagateSPIRVType()
174 Register Reg = MI->getOperand(0).getReg(); in propagateSPIRVType()
246 Def->getOperand(0).setReg(NewReg); in insertAssignInstr()
377 MI.getOperand(0).setReg(NewReg); in processInstr()
477 assert(MI.getOperand(1).isReg()); in processSwitches()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp61 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
69 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
115 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
116 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
747 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
763 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
777 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
791 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
835 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
849 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm11()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp142 Hi.getOperand(1).setOffset(Offset); in foldOffset()
144 Lo.getOperand(2).setOffset(Offset); in foldOffset()
148 MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg()); in foldOffset()
179 Register Rs = TailAdd.getOperand(1).getReg(); in foldLargeOffset()
180 Register Rt = TailAdd.getOperand(2).getReg(); in foldLargeOffset()
271 if (!OffsetTail.getOperand(1).isReg() || in foldShiftedOffset()
273 !OffsetTail.getOperand(2).isImm()) in foldShiftedOffset()
396 if (UseMI.getOperand(1).isFI()) in foldIntoMemoryOps()
467 Hi.getOperand(1).setOffset(NewOffset); in foldIntoMemoryOps()
468 MachineOperand &ImmOp = Lo.getOperand(2); in foldIntoMemoryOps()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp195 MIB.add(MI->getOperand(0)); in RevertWhileLoopSetup()
196 MIB.add(MI->getOperand(1)); in RevertWhileLoopSetup()
254 .add(WLSIt->getOperand(1)); in LowerWhileLoopStart()
472 VCTP->getOperand(0).getReg() != FirstVCTP->getOperand(0).getReg()) { in ConvertTailPredLoop()
588 MachineOperand &CondOP1 = Cond.getOperand(1), &CondOP2 = Cond.getOperand(2); in IsVPNOTEquivalent()
589 MachineOperand &PrevOP1 = Prev.getOperand(1), &PrevOP2 = Prev.getOperand(2); in IsVPNOTEquivalent()
1020 .add(MI.getOperand(0)) in ConvertVPSEL()
1021 .add(MI.getOperand(1)) in ConvertVPSEL()
1022 .add(MI.getOperand(1)) in ConvertVPSEL()
1024 .add(MI.getOperand(4)) in ConvertVPSEL()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
152 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
165 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
179 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
191 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
203 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp262 .add(I.getOperand(0)) in buildUnalignedStore()
343 .add(I.getOperand(0)) in select()
344 .add(I.getOperand(1)) in select()
355 .add(I.getOperand(0)) in select()
356 .add(I.getOperand(1)) in select()
362 .add(I.getOperand(0)) in select()
502 .add(I.getOperand(0)) in select()
538 .add(I.getOperand(0)) in select()
539 .add(I.getOperand(2)) in select()
540 .add(I.getOperand(1)) in select()
[all …]
H A DMipsSEISelLowering.cpp970 N->getOperand(1), N->getOperand(2)); in performSETCCCombine()
984 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
1608 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1623 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1627 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1668 Op->getOperand(1), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1891 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1901 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1951 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1969 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp228 if (MI.getOperand(3).getImm() != 0) in visitORR()
264 .add(SrcMI->getOperand(1)); in visitORR()
274 Register DefReg = MI.getOperand(0).getReg(); in visitORR()
275 Register SrcReg = MI.getOperand(2).getReg(); in visitORR()
320 .add(MI.getOperand(2)) in visitINSERT()
321 .add(MI.getOperand(3)); in visitINSERT()
554 MI.getOperand(0).setReg(DstReg); in splitTwoPartImm()
600 .add(MI.getOperand(1)) in visitINSviGPR()
601 .add(MI.getOperand(2)) in visitINSviGPR()
615 if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef()) in is64bitDefwithZeroHigh64bit()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2851 N0.getOperand(0) == N1.getOperand(1)) in visitADDLike()
2857 N0.getOperand(1) == N1.getOperand(0)) in visitADDLike()
2863 N0 == N1.getOperand(1).getOperand(0)) in visitADDLike()
2869 N0 == N1.getOperand(1).getOperand(1)) in visitADDLike()
2876 N0 == N1.getOperand(0).getOperand(1)) in visitADDLike()
3939 N0.getOperand(1).getOperand(0) == N1) in visitSUB()
3945 N0.getOperand(1).getOperand(1) == N1) in visitSUB()
5583 N00 = N0.getOperand(0).getOperand(0); in isSaturatingMinMax()
5584 N01 = N0.getOperand(0).getOperand(1); in isSaturatingMinMax()
16974 U->getOperand(0) == U->getOperand(1).getOperand(0) && in combineRepeatedFPDivisors()
[all …]

12345678910>>...44