Lines Matching refs:getOperand
52 MI.getOperand(3).getMetadata()->getOperand(0)) in addConstantsToTrack()
57 GR->add(GV, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
64 auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
69 BuildVec->getOperand(1 + i).getReg()); in addConstantsToTrack()
71 GR->add(Const, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
76 assert(MI.getOperand(2).isReg() && "Reg operand is expected"); in addConstantsToTrack()
77 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
85 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
88 auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg()); in addConstantsToTrack()
91 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg); in addConstantsToTrack()
107 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics()
108 MachineOperand &MOp = MI.getOperand(NumOp); in foldConstantsIntoIntrinsics()
113 ConstMI->getOperand(1).getCImm()->getZExtValue())); in foldConstantsIntoIntrinsics()
114 if (MRI.use_empty(ConstMI->getOperand(0).getReg())) in foldConstantsIntoIntrinsics()
131 assert(MI.getOperand(2).isReg()); in insertBitcasts()
135 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
138 Register Def = MI.getOperand(0).getReg(); in insertBitcasts()
139 Register Source = MI.getOperand(2).getReg(); in insertBitcasts()
141 getMDOperandAsType(MI.getOperand(3).getMetadata(), 0), MIB); in insertBitcasts()
144 addressSpaceToStorageClass(MI.getOperand(4).getImm())); in insertBitcasts()
173 if (MI->getOperand(0).isReg()) { in propagateSPIRVType()
174 Register Reg = MI->getOperand(0).getReg(); in propagateSPIRVType()
180 Type *Ty = MI->getOperand(1).getCImm()->getType(); in propagateSPIRVType()
186 Type *Ty = MI->getOperand(1).getGlobal()->getType(); in propagateSPIRVType()
194 MachineOperand &Op = MI->getOperand(1); in propagateSPIRVType()
246 Def->getOperand(0).setReg(NewReg); in insertAssignInstr()
266 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
269 getMDOperandAsType(MI.getOperand(2).getMetadata(), 0), MIB); in generateAssignInstrs()
272 addressSpaceToStorageClass(MI.getOperand(3).getImm())); in generateAssignInstrs()
279 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
280 Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0); in generateAssignInstrs()
295 Register Reg = MI.getOperand(0).getReg(); in generateAssignInstrs()
304 Ty = MI.getOperand(1).getCImm()->getType(); in generateAssignInstrs()
306 Ty = MI.getOperand(1).getFPImm()->getType(); in generateAssignInstrs()
310 MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in generateAssignInstrs()
314 ElemTy = ElemMI->getOperand(1).getCImm()->getType(); in generateAssignInstrs()
316 ElemTy = ElemMI->getOperand(1).getFPImm()->getType(); in generateAssignInstrs()
350 GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() == in createNewIdReg()
372 assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg())); in processInstr()
374 *(MRI.use_instr_begin(MI.getOperand(0).getReg())); in processInstr()
375 auto NewReg = createNewIdReg(MI.getOperand(0).getReg(), Opc, MRI, *GR).first; in processInstr()
376 AssignTypeInst.getOperand(1).setReg(NewReg); in processInstr()
377 MI.getOperand(0).setReg(NewReg); in processInstr()
410 Register SrcReg = MI.getOperand(1).getReg(); in processInstrsWithTypeFolding()
414 Register DstReg = MI.getOperand(0).getReg(); in processInstrsWithTypeFolding()
477 assert(MI.getOperand(1).isReg()); in processSwitches()
478 CompareRegs.insert(MI.getOperand(1).getReg()); in processSwitches()
484 if (MI.getOpcode() == TargetOpcode::G_SUB && MI.getOperand(1).isReg() && in processSwitches()
485 CompareRegs.contains(MI.getOperand(1).getReg())) { in processSwitches()
486 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg()); in processSwitches()
487 Register Dst = MI.getOperand(0).getReg(); in processSwitches()
493 if (MI.getOpcode() == TargetOpcode::G_ICMP && MI.getOperand(2).isReg() && in processSwitches()
494 CompareRegs.contains(MI.getOperand(2).getReg())) { in processSwitches()
495 Register Dst = MI.getOperand(0).getReg(); in processSwitches()
523 Register CompareReg = Switch->getOperand(1).getReg(); in processSwitches()
526 (*j)->getOperand(1).getReg() == CompareReg) in processSwitches()
530 (*j)->getOperand(2).getReg() == CompareReg)) in processSwitches()
534 Register Dst = ICMP->getOperand(0).getReg(); in processSwitches()
535 MachineOperand &PredOp = ICMP->getOperand(1); in processSwitches()
539 uint64_t Value = getIConstVal(ICMP->getOperand(3).getReg(), &MRI); in processSwitches()
541 assert(CBr->getOpcode() == SPIRV::G_BRCOND && CBr->getOperand(1).isMBB()); in processSwitches()
542 MachineBasicBlock *MBB = CBr->getOperand(1).getMBB(); in processSwitches()
553 NextMI->getOperand(0).isMBB()); in processSwitches()
554 MachineBasicBlock *NextMBB = NextMI->getOperand(0).getMBB(); in processSwitches()
558 (NextMBB->front().getOperand(2).isReg() && in processSwitches()
559 NextMBB->front().getOperand(2).getReg() != CompareReg)) { in processSwitches()
571 Register CReg = Switch->getOperand(k).getReg(); in processSwitches()
577 Values.push_back(ConstInstr->getOperand(1).getCImm()); in processSwitches()