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Searched refs:ZeroReg (Results 1 – 25 of 26) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
116 ZeroReg); in runOnMachineFunction()
122 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FrameLowering.cpp960 ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64() local
1012 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
1013 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
1014 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
1021 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp140 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
141 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3174 Register ZeroReg, RegisterOperand GPROpnd> {
3182 (Addiu ZeroReg, tglobaladdr:$in)>;
3184 (Addiu ZeroReg, tblockaddress:$in)>;
3186 (Addiu ZeroReg, tjumptable:$in)>;
3188 (Addiu ZeroReg, tconstpool:$in)>;
3190 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3192 (Addiu ZeroReg, texternalsym:$in)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
551 putConstant(I, ZeroReg, 0); in selectCmp()
556 ZeroReg)) in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1476 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1479 .addReg(ZeroReg).addImm(1) in SelectCmp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp950 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
951 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg || in LowerINLINEASM()
952 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) { in LowerINLINEASM()
980 Ops.push_back(ZeroReg); in LowerINLINEASM()
1931 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
1932 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg) in insertMultibyteShift()
1956 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg); in insertMultibyteShift()
1974 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
2008 ExtByte = ZeroReg; in insertMultibyteShift()
2050 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0); in insertMultibyteShift()
[all …]
H A DAVRExpandPseudoInsts.cpp459 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
483 .addReg(ZeroReg); in expand()
1494 Register ZeroReg = MI.getOperand(3).getReg(); in expandROLBRd() local
1513 .addReg(ZeroReg); in expandROLBRd()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2802 SrcReg = ZeroReg; in loadImmediate()
4259 unsigned ZeroReg; in expandDivRem() local
4264 ZeroReg = Mips::ZERO_64; in expandDivRem()
4268 ZeroReg = Mips::ZERO; in expandDivRem()
4292 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4299 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4305 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
4324 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4344 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4372 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4386 MIB.addReg(ZeroReg); in copyGPRRegTuple()
6996 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
7003 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
7025 .addReg(ZeroReg) in genAlternativeCodeSequence()
7053 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
7057 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
7063 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
7071 .addReg(ZeroReg) in genAlternativeCodeSequence()
7106 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
7113 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64InstrInfo.h194 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64ExpandPseudoInsts.cpp79 unsigned ExtendImm, unsigned ZeroReg,
224 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
257 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64ISelDAGToDAG.cpp3630 unsigned ZeroReg; in tryShiftAmountMod() local
3634 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3638 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3641 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
3650 unsigned ZeroReg; in tryShiftAmountMod() local
3654 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3658 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3661 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64FastISel.cpp383 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
386 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4925 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4928 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1054 uint16_t ZeroReg = readU16(); in executeMatchTable() local
1058 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
1064 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1491 Register ZeroReg = in legalizeIntrinsic() local
1494 {MidReg, ZeroReg}) in legalizeIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp1104 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect() local
1115 .addUse(ZeroReg) in selectSelect()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2083 MCRegister ZeroReg; in onlyFoldImmediate() local
2086 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2088 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2094 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelLowering.cpp12049 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
12116 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
12161 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
12204 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
13082 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
13114 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
13171 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
13195 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
H A DPPCISelDAGToDAG.cpp6299 SDValue ZeroReg = in Select() local
6322 Subtarget->isLittleEndian() ? PPC::LVSR : PPC::LVSL, dl, Type, ZeroReg, in Select()
6327 {ZeroReg, N->getOperand(1), N->getOperand(0)}); in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2155 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
2157 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
2158 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
2159 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp8693 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
8695 ZeroReg, 0); in convertNonUniformLoopRegion()
8696 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()

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