Lines Matching refs:ZeroReg
950 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
951 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg || in LowerINLINEASM()
952 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) { in LowerINLINEASM()
980 Ops.push_back(ZeroReg); in LowerINLINEASM()
1931 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
1932 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg) in insertMultibyteShift()
1956 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg); in insertMultibyteShift()
1974 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
2008 ExtByte = ZeroReg; in insertMultibyteShift()
2050 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0); in insertMultibyteShift()
2072 ShrExtendReg = ZeroReg; in insertMultibyteShift()