Lines Matching refs:ZeroReg
4371 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
4386 MIB.addReg(ZeroReg); in copyGPRRegTuple()
5882 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
5901 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
5915 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
5916 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
6056 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
6058 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
6991 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
6996 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
7003 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
7025 .addReg(ZeroReg) in genAlternativeCodeSequence()
7053 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
7057 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
7063 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
7071 .addReg(ZeroReg) in genAlternativeCodeSequence()
7101 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
7106 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
7113 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
7134 .addReg(ZeroReg) in genAlternativeCodeSequence()