Home
last modified time | relevance | path

Searched refs:WR4 (Results 1 – 25 of 82) sorted by relevance

1234

/freebsd-14.2/sys/arm/freescale/imx/
H A Dimx6_ccm.c95 WR4(sc, CCM_CCGR0, reg); in ccm_init_gates()
100 WR4(sc, CCM_CCGR1, reg); in ccm_init_gates()
107 WR4(sc, CCM_CCGR2, reg); in ccm_init_gates()
112 WR4(sc, CCM_CCGR3, reg); in ccm_init_gates()
117 WR4(sc, CCM_CCGR4, reg); in ccm_init_gates()
122 WR4(sc, CCM_CCGR5, reg); in ccm_init_gates()
127 WR4(sc, CCM_CCGR6, reg); in ccm_init_gates()
179 WR4(sc, CCM_CGPR, reg); in ccm_attach()
182 WR4(sc, CCM_CLPCR, reg); in ccm_attach()
453 WR4(sc, CCM_CCGR3, reg); in imx_ccm_ipu_enable()
[all …]
/freebsd-14.2/sys/arm/nvidia/drm2/
H A Dtegra_dc.c432 WR4(sc, DC_WIN_DDA_INCREMENT, in dc_setup_window()
442 WR4(sc, DC_WIN_LINE_STRIDE, in dc_setup_window()
665 WR4(sc, DC_DISP_REF_TO_SYNC, in dc_crtc_mode_set()
669 WR4(sc, DC_DISP_SYNC_WIDTH, in dc_crtc_mode_set()
673 WR4(sc, DC_DISP_BACK_PORCH, in dc_crtc_mode_set()
677 WR4(sc, DC_DISP_FRONT_PORCH, in dc_crtc_mode_set()
681 WR4(sc, DC_DISP_DISP_ACTIVE, in dc_crtc_mode_set()
757 WR4(sc, DC_CMD_INT_MASK, in dc_crtc_prepare()
761 WR4(sc, DC_CMD_INT_ENABLE, in dc_crtc_prepare()
1210 WR4(sc, DC_CMD_INT_TYPE, in dc_init_client()
[all …]
H A Dtegra_hdmi.c554 WR4(sc, HDMI_NV_PDISP_AUDIO_N, in audio_setup()
565 WR4(sc, HDMI_NV_PDISP_HDMI_SPARE, in audio_setup()
570 WR4(sc, HDMI_NV_PDISP_AUDIO_N, val); in audio_setup()
572 WR4(sc, aval_reg, audio_aval); in audio_setup()
670 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_sor_start()
675 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_sor_start()
678 WR4(sc, HDMI_NV_PDISP_SOR_PWR, 0); in hdmi_sor_start()
705 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0); in hdmi_sor_start()
712 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0); in hdmi_sor_start()
742 WR4(sc, HDMI_NV_PDISP_INT_MASK, 0); in hdmi_disable()
[all …]
/freebsd-14.2/sys/arm/xilinx/
H A Duart_dev_cdnc.c57 #define WR4(bas, reg, value) \ macro
270 WR4(bas, CDNC_UART_CTRL_REG, in cdnc_uart_hw_init()
278 WR4(bas, CDNC_UART_MODEM_STAT_REG, in cdnc_uart_hw_init()
284 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); in cdnc_uart_hw_init()
290 WR4(bas, CDNC_UART_CTRL_REG, in cdnc_uart_hw_init()
338 WR4(bas, CDNC_UART_FIFO, c); in cdnc_uart_putc()
446 WR4(bas, CDNC_UART_IEN_REG, in cdnc_uart_bus_attach()
518 WR4(bas, CDNC_UART_ISTAT_REG, in cdnc_uart_bus_receive()
593 WR4(bas, CDNC_UART_MODEM_STAT_REG, in cdnc_uart_bus_ipend()
682 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, in cdnc_uart_bus_grab()
[all …]
H A Dzy7_qspi.c251 WR4(sc, ZY7_QSPI_TXD1_REG, data); in zy7_qspi_write_fifo()
254 WR4(sc, ZY7_QSPI_TXD2_REG, data); in zy7_qspi_write_fifo()
257 WR4(sc, ZY7_QSPI_TXD3_REG, data); in zy7_qspi_write_fifo()
321 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_abort_transfer()
351 WR4(sc, ZY7_QSPI_INTR_STAT_REG, in zy7_qspi_intr()
361 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_intr()
375 WR4(sc, ZY7_QSPI_INTR_STAT_REG, in zy7_qspi_intr()
390 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_intr()
392 WR4(sc, ZY7_QSPI_INTR_EN_REG, in zy7_qspi_intr()
626 WR4(sc, ZY7_QSPI_EN_REG, 0); in zy7_qspi_detach()
[all …]
H A Dzy7_spi.c207 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_abort_transfer()
237 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
247 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
257 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
271 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
273 WR4(sc, ZY7_SPI_INTR_EN_REG, in zy7_spi_intr()
320 WR4(sc, ZY7_SPI_TX_THRESH_REG, 32); in zy7_spi_init_hw()
321 WR4(sc, ZY7_SPI_RX_THRESH_REG, 1); in zy7_spi_init_hw()
325 WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0); in zy7_spi_init_hw()
463 WR4(sc, ZY7_SPI_EN_REG, 0); in zy7_spi_detach()
[all …]
H A Dzy7_devcfg.c403 WR4(sc, ZY7_DEVCFG_CTRL, in zy7_devcfg_init_hw()
437 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
446 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); in zy7_devcfg_reset_pl()
457 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
474 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
592 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR, in zy7_devcfg_write()
595 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR, in zy7_devcfg_write()
599 WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4); in zy7_devcfg_write()
600 WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0); in zy7_devcfg_write()
654 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); in zy7_devcfg_intr()
[all …]
H A Dzy7_slcr.c123 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); in zy7_slcr_lock()
137 WR4(sc, ZY7_SLCR_REBOOT_STAT, in zy7_slcr_cpu_reset()
167 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); in zy7_slcr_preload_pl()
198 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); in zy7_slcr_postload_pl()
275 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_source()
367 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_freq()
446 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); in zy7_pl_fclk_enable()
447 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0); in zy7_pl_fclk_enable()
470 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); in zy7_pl_fclk_disable()
471 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1); in zy7_pl_fclk_disable()
[all …]
/freebsd-14.2/sys/dev/ffec/
H A Dif_ffec.c437 WR4(sc, FEC_RCR_REG, rcr); in ffec_miibus_statchg()
438 WR4(sc, FEC_TCR_REG, tcr); in ffec_miibus_statchg()
439 WR4(sc, FEC_ECR_REG, ecr); in ffec_miibus_statchg()
496 WR4(sc, FEC_IEEE_R_DROP, 0); in ffec_clear_stats()
499 WR4(sc, FEC_RMON_R_FRAG, 0); in ffec_clear_stats()
500 WR4(sc, FEC_RMON_R_JAB, 0); in ffec_clear_stats()
505 WR4(sc, FEC_RMON_T_COL, 0); in ffec_clear_stats()
507 WR4(sc, FEC_RMON_T_FRAG, 0); in ffec_clear_stats()
508 WR4(sc, FEC_RMON_T_JAB, 0); in ffec_clear_stats()
1164 WR4(sc, FEC_TCR_REG, 0); in ffec_init_locked()
[all …]
/freebsd-14.2/sys/arm64/broadcom/genet/
H A Dif_genet.c474 WR4(sc, GENET_UMAC_CMD, 0); in gen_reset()
475 WR4(sc, GENET_UMAC_CMD, in gen_reset()
478 WR4(sc, GENET_UMAC_CMD, 0); in gen_reset()
494 WR4(sc, GENET_RBUF_CTRL, val); in gen_enable()
502 WR4(sc, GENET_UMAC_CMD, val); in gen_enable()
526 WR4(sc, GENET_UMAC_CMD, val); in gen_disable()
531 WR4(sc, GENET_UMAC_CMD, val); in gen_disable()
981 WR4(sc, GENET_UMAC_CMD, cmd); in gen_setup_rxfilter()
1001 WR4(sc, GENET_UMAC_MAC0, val); in gen_set_enaddr()
1003 WR4(sc, GENET_UMAC_MAC1, val); in gen_set_enaddr()
[all …]
/freebsd-14.2/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1015 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
1054 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1059 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1064 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1082 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_enable()
1094 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_disable()
1114 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_enable()
1126 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_disable()
1279 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); in usb2_enable()
1382 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_enable()
[all …]
H A Dtegra210_clk_pll.c767 WR4(sc, PLLE_AUX, reg); in plle_enable()
823 WR4(sc, PLLE_AUX, reg); in plle_enable()
827 WR4(sc, PLLE_AUX, reg); in plle_enable()
1165 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1171 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1176 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1199 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1229 WR4(sc, PLLX_MISC, reg); in pllx_init()
1235 WR4(sc, PLLX_MISC_2, reg); in pllx_init()
1239 WR4(sc, PLLX_MISC_4, reg); in pllx_init()
[all …]
/freebsd-14.2/sys/arm/nvidia/
H A Dtegra_i2c.c244 WR4(sc, I2C_FIFO_CONTROL, reg); in tegra_i2c_flush_fifo()
272 WR4(sc, I2C_CLK_DIVISOR, in tegra_i2c_setup_clk()
283 WR4(sc, I2C_BUS_CLEAR_CONFIG, in tegra_i2c_bus_clear()
298 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg); in tegra_i2c_bus_clear()
332 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_hw_init()
374 WR4(sc, I2C_TX_PACKET_FIFO, reg); in tegra_i2c_tx()
423 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_intr()
467 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_intr()
484 WR4(sc, I2C_TX_PACKET_FIFO, tmp); in tegra_i2c_start_msg()
502 WR4(sc, I2C_TX_PACKET_FIFO, tmp); in tegra_i2c_start_msg()
[all …]
H A Dtegra_usbphy.c356 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
360 WR4(sc, UTMIP_TX_CFG0, val); in usbphy_utmi_enable()
367 WR4(sc, UTMIP_HSRX_CFG0, val); in usbphy_utmi_enable()
372 WR4(sc, UTMIP_HSRX_CFG1, val); in usbphy_utmi_enable()
381 WR4(sc, UTMIP_MISC_CFG0, val); in usbphy_utmi_enable()
451 WR4(sc, UTMIP_XCVR_CFG0, val); in usbphy_utmi_enable()
459 WR4(sc, UTMIP_XCVR_CFG1, val); in usbphy_utmi_enable()
464 WR4(sc, UTMIP_BIAS_CFG1, val); in usbphy_utmi_enable()
471 WR4(sc, UTMIP_SPARE_CFG0, val); in usbphy_utmi_enable()
527 WR4(sc, UTMIP_XCVR_CFG0, val); in usbphy_utmi_disable()
[all …]
/freebsd-14.2/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c376 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
392 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
397 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
402 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
443 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_powerup()
455 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_powerdown()
502 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_powerup()
506 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_powerup()
518 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_powerdown()
647 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in phy_powerup()
[all …]
H A Dtegra124_clk_pll.c422 WR4(sc, sc->base_reg, reg); in pll_enable()
435 WR4(sc, sc->base_reg, reg); in pll_disable()
569 WR4(sc, sc->base_reg, reg); in plle_enable()
574 WR4(sc, PLLE_AUX, reg); in plle_enable()
584 WR4(sc, sc->misc_reg, reg); in plle_enable()
589 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
595 WR4(sc, sc->base_reg, reg); in plle_enable()
608 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
611 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
628 WR4(sc, PLLE_AUX, reg); in plle_enable()
[all …]
/freebsd-14.2/sys/dev/eqos/
H A Dif_eqos.c121 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); in eqos_miibus_readreg()
148 WR4(sc, GMAC_MAC_MDIO_DATA, val); in eqos_miibus_writereg()
154 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); in eqos_miibus_writereg()
217 WR4(sc, GMAC_MAC_CONFIGURATION, reg); in eqos_miibus_statchg()
372 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, in eqos_enable_intr()
442 WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); in eqos_setup_rxfilter()
474 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR, in eqos_init_rings()
480 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR, in eqos_init_rings()
484 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, in eqos_init_rings()
524 WR4(sc, GMAC_MMC_CONTROL, in eqos_init()
[all …]
/freebsd-14.2/sys/arm64/rockchip/
H A Drk_tsadc.c484 WR4(sc, TSADC_INT_EN, val); in tsadc_init_tsensor()
491 WR4(sc, TSADC_AUTO_CON, val); in tsadc_init_tsensor()
498 WR4(sc, TSADC_INT_EN, val); in tsadc_init_tsensor()
514 WR4(sc, TSADC_AUTO_CON, val); in tsadc_init()
521 WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); in tsadc_init()
522 WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); in tsadc_init()
544 WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); in tsadc_init()
545 WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); in tsadc_init()
551 WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); in tsadc_init()
672 WR4(sc, TSADC_INT_PD, val); in tsadc_intr()
[all …]
/freebsd-14.2/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c58 #define WR4 (sc->write) macro
501 WR4(sc, off & ~3, val32); in sdhci_fsl_fdt_write_1()
544 WR4(sc, off & ~3, val32); in sdhci_fsl_fdt_write_2()
573 WR4(sc, off, val); in sdhci_fsl_fdt_write_4()
1138 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_switch_tuning_block()
1162 WR4(sc, SDHCI_FSL_TBPTR, reg); in sdhci_fsl_sw_tuning()
1178 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_sw_tuning()
1250 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_fdt_tune()
1363 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_disable_hs400_mode()
1381 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_disable_hs400_mode()
[all …]
H A Dfsl_sdhci.c398 WR4(sc, SDHC_PROT_CTRL, val32); in fsl_sdhci_write_1()
416 WR4(sc, off & ~3, val32); in fsl_sdhci_write_1()
476 WR4(sc, USDHC_MIX_CONTROL, val32); in fsl_sdhci_write_2()
487 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); in fsl_sdhci_write_2()
495 WR4(sc, off & ~3, val32); in fsl_sdhci_write_2()
508 WR4(sc, off, val); in fsl_sdhci_write_4()
645 WR4(sc, SDHCI_CLOCK_CONTROL, val32); in fsl_sdhc_set_clock()
742 WR4(sc, SDHCI_INT_STATUS, intmask); in fsl_sdhci_intr()
892 WR4(sc, SDHC_WTMK_LVL, 0x10801080); in fsl_sdhci_attach()
894 WR4(sc, SDHC_WTMK_LVL, 0x08800880); in fsl_sdhci_attach()
[all …]
/freebsd-14.2/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c279 WR4(sc, off & ~3, val32); in WR2()
290 WR4(sc, off & ~3, val32); in WR1()
346 WR4(sc, HC_POWER, 0); in bcm_sdhost_reset()
348 WR4(sc, HC_COMMAND, 0); in bcm_sdhost_reset()
349 WR4(sc, HC_ARGUMENT, 0); in bcm_sdhost_reset()
354 WR4(sc, HC_BLOCKSIZE, 0); in bcm_sdhost_reset()
362 WR4(sc, HC_DEBUG, dbg); in bcm_sdhost_reset()
366 WR4(sc, HC_POWER, 1); in bcm_sdhost_reset()
534 WR4(sc, HC_COMMAND, in bcm_sdhost_waitcommand_status()
616 WR4(sc, HC_COMMAND, in bcm_sdhost_intr()
[all …]
/freebsd-14.2/sys/arm64/qoriq/
H A Dqoriq_therm.c315 WR4(sc, TMU_TTRCR(i), ranges[i]); in qoriq_therm_fdt_calib()
326 WR4(sc, TMU_TTCFGR, calibs[i]); in qoriq_therm_fdt_calib()
327 WR4(sc, TMU_TSCFGR, calibs[i + 1]); in qoriq_therm_fdt_calib()
423 WR4(sc, TMU_TMR, 0); in qoriq_therm_attach()
427 WR4(sc, TMU_TIER, 0); in qoriq_therm_attach()
431 WR4(sc, TMUV1_TMTMIR, 0x0F); in qoriq_therm_attach()
433 WR4(sc, TMUV2_TMTMIR, 0x0F); /* disable */ in qoriq_therm_attach()
435 WR4(sc, TMUV2_TEUMR(0), 0x51009c00); in qoriq_therm_attach()
452 WR4(sc, TMU_TMR, 0x8C000000 | sites); in qoriq_therm_attach()
456 WR4(sc, TMUV2_TMSR, sites); in qoriq_therm_attach()
[all …]
/freebsd-14.2/sys/arm/mv/
H A Dmv_cp110_icu.c162 WR4(sc, ICU_INT_CFG(i), 0); in mv_cp110_icu_attach()
250 WR4(sc, ICU_SETSPI_NSR_AL, addr & UINT32_MAX); in mv_cp110_icu_init()
251 WR4(sc, ICU_SETSPI_NSR_AH, (addr >> 32) & UINT32_MAX); in mv_cp110_icu_init()
253 WR4(sc, ICU_CLRSPI_NSR_AL, addr & UINT32_MAX); in mv_cp110_icu_init()
254 WR4(sc, ICU_CLRSPI_NSR_AH, (addr >> 32) & UINT32_MAX); in mv_cp110_icu_init()
257 WR4(sc, ICU_SETSPI_SEI_AL, addr & UINT32_MAX); in mv_cp110_icu_init()
258 WR4(sc, ICU_SETSPI_SEI_AH, (addr >> 32) & UINT32_MAX); in mv_cp110_icu_init()
320 WR4(sc, ICU_INT_CFG(irq_no), vector); in mv_cp110_icu_map_intr()
330 WR4(sc, ICU_INT_CFG(ICU_INT_SATA1), vector); in mv_cp110_icu_map_intr()
332 WR4(sc, ICU_INT_CFG(ICU_INT_SATA0), vector); in mv_cp110_icu_map_intr()
[all …]
/freebsd-14.2/sys/dev/hwpmc/
H A Dpmu_dmc620.c70 #define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v)) macro
71 #define MD4(sc, r, c, s) WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s))
99 WR4(sc, DMC620_REG(cntr, reg), val); in pmu_dmc620_wr4()
155 WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0); in pmu_dmc620_acpi_attach()
156 WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0); in pmu_dmc620_acpi_attach()
224 WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL), in pmu_dmc620_counter_overflow_intr()
234 WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0); in pmu_dmc620_counter_overflow_intr()
242 WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0); in pmu_dmc620_counter_overflow_intr()
247 WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL), in pmu_dmc620_counter_overflow_intr()
/freebsd-14.2/sys/dev/cadence/
H A Dif_cgem.c288 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); in cgem_get_mac()
360 WR4(sc, CGEM_HASH_TOP, hashes[0]); in cgem_rx_filter()
361 WR4(sc, CGEM_HASH_BOT, hashes[1]); in cgem_rx_filter()
992 WR4(sc, CGEM_INTR_STAT, istatus); in cgem_intr()
1051 WR4(sc, CGEM_NET_CTRL, 0); in cgem_reset()
1057 WR4(sc, CGEM_HASH_BOT, 0); in cgem_reset()
1058 WR4(sc, CGEM_HASH_TOP, 0); in cgem_reset()
1060 WR4(sc, CGEM_RX_QBAR, 0); in cgem_reset()
1114 WR4(sc, CGEM_DMA_CFG, dma_cfg); in cgem_config()
1290 WR4(sc, CGEM_DMA_CFG, in cgem_ioctl()
[all …]

1234