232 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)  in WR4()  function
325 	WR4(sc, FEC_IER_REG, FEC_IER_MII);  in ffec_miibus_readreg()
327 	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |  in ffec_miibus_readreg()
349 	WR4(sc, FEC_IER_REG, FEC_IER_MII);  in ffec_miibus_writereg()
351 	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |  in ffec_miibus_writereg()
437 	WR4(sc, FEC_RCR_REG, rcr);  in ffec_miibus_statchg()
438 	WR4(sc, FEC_TCR_REG, tcr);  in ffec_miibus_statchg()
439 	WR4(sc, FEC_ECR_REG, ecr);  in ffec_miibus_statchg()
491 		WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);  in ffec_clear_stats()
492 		WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR);  in ffec_clear_stats()
494 		WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS);  in ffec_clear_stats()
496 		WR4(sc, FEC_IEEE_R_DROP, 0);  in ffec_clear_stats()
497 		WR4(sc, FEC_IEEE_R_MACERR, 0);  in ffec_clear_stats()
498 		WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);  in ffec_clear_stats()
499 		WR4(sc, FEC_RMON_R_FRAG, 0);  in ffec_clear_stats()
500 		WR4(sc, FEC_RMON_R_JAB, 0);  in ffec_clear_stats()
501 		WR4(sc, FEC_RMON_R_MC_PKT, 0);  in ffec_clear_stats()
502 		WR4(sc, FEC_RMON_R_OVERSIZE, 0);  in ffec_clear_stats()
503 		WR4(sc, FEC_RMON_R_PACKETS, 0);  in ffec_clear_stats()
504 		WR4(sc, FEC_RMON_R_UNDERSIZE, 0);  in ffec_clear_stats()
505 		WR4(sc, FEC_RMON_T_COL, 0);  in ffec_clear_stats()
506 		WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);  in ffec_clear_stats()
507 		WR4(sc, FEC_RMON_T_FRAG, 0);  in ffec_clear_stats()
508 		WR4(sc, FEC_RMON_T_JAB, 0);  in ffec_clear_stats()
509 		WR4(sc, FEC_RMON_T_MC_PKT, 0);  in ffec_clear_stats()
510 		WR4(sc, FEC_RMON_T_OVERSIZE , 0);  in ffec_clear_stats()
511 		WR4(sc, FEC_RMON_T_PACKETS, 0);  in ffec_clear_stats()
512 		WR4(sc, FEC_RMON_T_UNDERSIZE, 0);  in ffec_clear_stats()
514 		WR4(sc, FEC_MIBC_REG, mibc);  in ffec_clear_stats()
686 		WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);  in ffec_txstart_locked()
931 		WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);  in ffec_rxfinish_locked()
1010 	WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));  in ffec_setup_rxfilter()
1011 	WR4(sc, FEC_GALR_REG, (uint32_t)ghash);  in ffec_setup_rxfilter()
1025 	WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));  in ffec_setup_rxfilter()
1026 	WR4(sc, FEC_IALR_REG, (uint32_t)ihash);  in ffec_setup_rxfilter()
1032 	WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |  in ffec_setup_rxfilter()
1034 	WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));  in ffec_setup_rxfilter()
1055 	WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);  in ffec_stop_locked()
1056 	WR4(sc, FEC_IEM_REG, 0x00000000);  in ffec_stop_locked()
1057 	WR4(sc, FEC_IER_REG, 0xffffffff);  in ffec_stop_locked()
1132 	WR4(sc, FEC_IEM_REG, 0x00000000);  in ffec_init_locked()
1133 	WR4(sc, FEC_IER_REG, 0xffffffff);  in ffec_init_locked()
1150 	WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);  in ffec_init_locked()
1156 	WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));  in ffec_init_locked()
1164 	WR4(sc, FEC_TCR_REG, 0);  in ffec_init_locked()
1171 	WR4(sc, FEC_OPD_REG, 0x00010020);  in ffec_init_locked()
1195 	WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);  in ffec_init_locked()
1202 	WR4(sc, FEC_FTRL_REG, maxfl);  in ffec_init_locked()
1214 	WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);  in ffec_init_locked()
1215 	WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);  in ffec_init_locked()
1224 	WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);  in ffec_init_locked()
1231 	WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);  in ffec_init_locked()
1233 	WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);  in ffec_init_locked()
1240 		WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16);  in ffec_init_locked()
1257 	WR4(sc, FEC_ECR_REG, regval);  in ffec_init_locked()
1272 	WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);  in ffec_init_locked()
1298 		WR4(sc, FEC_IER_REG, FEC_IER_TXF);  in ffec_intr()
1303 		WR4(sc, FEC_IER_REG, FEC_IER_RXF);  in ffec_intr()
1316 		WR4(sc, FEC_IER_REG, FEC_IER_EBERR);  in ffec_intr()
1687 		WR4(sc, FEC_ECR_REG, 0);  in ffec_attach()
1689 		WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);  in ffec_attach()
1736 	WR4(sc, FEC_MSCR_REG, mscr);  in ffec_attach()