98 #define	WR4(sc, o, v)		bus_write_4(sc->res[EQOS_RES_MEM], (o), (v))  macro
121 	WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);  in eqos_miibus_readreg()
148 	WR4(sc, GMAC_MAC_MDIO_DATA, val);  in eqos_miibus_writereg()
154 	WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);  in eqos_miibus_writereg()
217 	WR4(sc, GMAC_MAC_CONFIGURATION, reg);  in eqos_miibus_statchg()
221 	WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1);  in eqos_miibus_statchg()
372 	WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE,  in eqos_enable_intr()
382 	WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0);  in eqos_disable_intr()
439 	WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val);  in eqos_setup_rxfilter()
442 	WR4(sc, GMAC_MAC_ADDRESS0_LOW, val);  in eqos_setup_rxfilter()
445 	WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[1]);  in eqos_setup_rxfilter()
446 	WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[0]);  in eqos_setup_rxfilter()
449 	WR4(sc, GMAC_MAC_PACKET_FILTER, pfil);  in eqos_setup_rxfilter()
458 	WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR);  in eqos_reset()
472 	WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI,  in eqos_init_rings()
474 	WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR,  in eqos_init_rings()
476 	WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1);  in eqos_init_rings()
478 	WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI,  in eqos_init_rings()
480 	WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR,  in eqos_init_rings()
482 	WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1);  in eqos_init_rings()
484 	WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,  in eqos_init_rings()
505 	WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1);  in eqos_init()
512 	WR4(sc, GMAC_DMA_CHAN0_CONTROL, val);  in eqos_init()
516 	WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);  in eqos_init()
521 	WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);  in eqos_init()
524 	WR4(sc, GMAC_MMC_CONTROL,  in eqos_init()
530 	WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE,  in eqos_init()
533 	WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE,  in eqos_init()
542 	WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, val);  in eqos_init()
545 	WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val);  in eqos_init()
548 	WR4(sc, GMAC_RXQ_CTRL0, (GMAC_RXQ_CTRL0_EN_MASK << 16) |  in eqos_init()
559 	WR4(sc, GMAC_MAC_CONFIGURATION, val);  in eqos_init()
609 		WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR,  in eqos_start_locked()
641 	WR4(sc, GMAC_MAC_CONFIGURATION, val);  in eqos_stop()
646 	WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);  in eqos_stop()
651 	WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);  in eqos_stop()
656 	WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);  in eqos_stop()
669 	WR4(sc, GMAC_MAC_CONFIGURATION, val);  in eqos_stop()
722 		WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,  in eqos_rxintr()
792 			WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, mtl_clear);  in eqos_intr_mtl()
844 		WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status);  in eqos_intr()
980 	WR4(sc, GMAC_DMA_SYSBUS_MODE, val);  in eqos_axi_configure()