| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 86 unsigned SubReg = AMDGPU::NoSubRegister; member
283 for (auto [SubReg, SRI] : SubRegs) in getRegClassWithShiftedSubregs()
299 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
311 CoverSubreg = SubReg; in getMinSizeReg()
323 for (auto [SubReg, SRI] : SubRegs) in getMinSizeReg()
327 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
390 if (unsigned NewSubReg = I->second.SubReg) in updateLiveIntervals()
426 const unsigned SubReg = MO.getSubReg(); in rewriteReg() local
434 SubRegRC = TRI->getSubRegisterClass(RC, SubReg); in rewriteReg()
469 unsigned SubReg = SubRegs[MO.getSubReg()].SubReg; in rewriteReg() local
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| H A D | SIRegisterInfo.h | 317 unsigned SubReg,
366 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
388 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg() argument
389 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getChannelFromSubReg()
393 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg() argument
394 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
451 unsigned SubReg) const;
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| H A D | SIShrinkInstructions.cpp | 56 Register Reg, unsigned SubReg) const;
58 unsigned SubReg) const;
60 unsigned SubReg) const;
561 unsigned SubReg) const { in instAccessReg()
580 unsigned SubReg) const { in instReadsReg()
581 return instAccessReg(MI->uses(), Reg, SubReg); in instReadsReg()
586 return instAccessReg(MI->defs(), Reg, SubReg); in instModifiesReg()
722 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
723 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
724 .addReg(Y1.Reg, 0, Y1.SubReg) in matchSwap()
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| H A D | SIPreAllocateWWMRegs.cpp | 133 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
134 if (SubReg != 0) { in rewriteRegs()
135 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
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| H A D | SIRegisterInfo.cpp | 1533 Register SubReg = e == 1 in buildSpillLoadStore() local
1602 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1620 SubReg = TmpIntermediateVGPR; in buildSpillLoadStore()
1774 Register SubReg = in spillSGPR() local
1828 Register SubReg = in spillSGPR() local
1890 Register SubReg = in restoreSGPR() local
1923 Register SubReg = in restoreSGPR() local
1970 Register SubReg = in spillEmergencySGPR() local
2005 Register SubReg = in spillEmergencySGPR() local
2011 SubReg) in spillEmergencySGPR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 200 LastDefReg = SubReg; in FindLastPartialDef()
216 PartDefRegs.insert(SubReg); in FindLastPartialDef()
246 if (Processed.count(SubReg)) in HandlePhysRegUse()
268 PhysRegUse[SubReg] = &MI; in HandlePhysRegUse()
360 if (!PartUses.count(SubReg)) in HandlePhysRegKill()
437 Live.insert(SubReg); in HandlePhysRegDef()
446 if (Live.count(SubReg)) in HandlePhysRegDef()
448 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) { in HandlePhysRegDef()
460 if (!Live.count(SubReg)) in HandlePhysRegDef()
463 HandlePhysRegKill(SubReg, MI); in HandlePhysRegDef()
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| H A D | LiveIntervalCalc.cpp | 58 unsigned SubReg = MO.getSubReg(); in calculate() local
59 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
60 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
158 unsigned SubReg = MO.getSubReg(); in extendToUses() local
159 if (SubReg != 0) { in extendToUses()
160 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| H A D | PeepholeOptimizer.cpp | 341 addSource(Reg, SubReg); in ValueTrackerResult()
376 return RegSrcs[Idx].SubReg; in getSrcSubReg()
801 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
835 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1117 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1179 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1190 LookupSrc.SubReg = Res.getSrcSubReg(0); in getNewSource()
1300 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1302 if (Def.SubReg) { in rewriteSource()
2035 BaseReg.SubReg) in getNextSourceFromInsertSubreg()
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| H A D | MachineInstrBundle.cpp | 200 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in finalizeBundle() local
201 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
202 LocalDefs.push_back(SubReg); in finalizeBundle()
320 unsigned SubReg = MO.getSubReg(); in AnalyzeVirtRegLanesInBundle() local
321 if (SubReg == 0 && MO.isUse() && !MO.isUndef()) in AnalyzeVirtRegLanesInBundle()
324 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in AnalyzeVirtRegLanesInBundle()
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| H A D | DetectDeadLanes.cpp | 92 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
93 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
366 if (SubReg == 0) in determineInitialUsedLanes()
369 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
419 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
420 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
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| H A D | LiveIntervals.cpp | 559 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
560 if (SubReg != 0) { in shrinkToUses()
777 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
778 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1019 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1020 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1036 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1037 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1450 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1451 if (SubReg != 0 && LaneMask.any() in findLastUseBefore()
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| H A D | LiveRangeEdit.cpp | 140 unsigned SubReg = MO.getSubReg(); in allUsesAvailableAt() local
141 LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in allUsesAvailableAt()
273 unsigned SubReg = MO.getSubReg(); in useIsKill() local
274 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
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| H A D | CriticalAntiDepBreaker.cpp | 216 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in PrescanInstruction() local
217 KeepRegs.set(SubReg); in PrescanInstruction()
240 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) { in PrescanInstruction() local
241 KeepRegs.set(SubReg); in PrescanInstruction()
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| H A D | LiveDebugVariables.cpp | 543 unsigned SubReg; /// Qualifiying subregister for Reg. member
1282 unsigned SubReg = Position.SubReg; in runOnMachineFunction() local
1284 PHIValPos VP = {SI, Reg, SubReg}; in runOnMachineFunction()
1839 unsigned SubReg = It.second.SubReg; in emitDebugValues() local
1845 if (SubReg != 0) in emitDebugValues()
1846 PhysReg = TRI->getSubReg(PhysReg, SubReg); in emitDebugValues()
1858 if (SubReg) in emitDebugValues()
1859 regSizeInBits = TRI->getSubRegIdxSize(SubReg); in emitDebugValues()
1865 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
1880 dbgs() << "DBG_PHI for Vreg " << Reg << " subreg " << SubReg << in emitDebugValues()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
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| H A D | AArch64RegisterInfo.cpp | 333 for (MCPhysReg SubReg : in UpdateCustomCallPreservedMask() local
337 UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32); in UpdateCustomCallPreservedMask()
442 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA)) in getStrictlyReservedRegs() local
443 Reserved.set(SubReg); in getStrictlyReservedRegs()
447 for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true); in getStrictlyReservedRegs() local
448 SubReg.isValid(); ++SubReg) in getStrictlyReservedRegs()
449 Reserved.set(*SubReg); in getStrictlyReservedRegs()
1019 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
1054 if (MI->isCopy() && SubReg != DstSubReg && in shouldCoalesce()
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| /freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 257 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
351 for (const auto &SubReg : Map) in computeSubRegs() local
353 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
358 if (SubReg.second == this) { in computeSubRegs()
372 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
373 if (Ins->second == SubReg.first) in computeSubRegs()
476 const CodeGenRegister *SubReg; in computeSecondarySubRegs() local
552 for (auto SubReg : SubRegs) in computeSuperRegs() local
558 for (auto SubReg : SubRegs) { in computeSuperRegs() local
583 for (auto SubReg : SubRegs) in addSubRegsPreOrder() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 47 MCRegister SubReg) const { in getSubRegIndex()
48 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
53 if (Sub == SubReg) in getSubRegIndex()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 503 unsigned SubReg; member
505 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
506 : Reg(Reg), SubReg(SubReg) {} in Reg()
509 return Reg == P.Reg && SubReg == P.SubReg;
522 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
524 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
2250 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2257 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
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| H A D | LivePhysRegs.h | 84 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg() local
85 LiveRegs.insert(SubReg); in addReg()
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| H A D | MachineInstrBuilder.h | 99 unsigned SubReg = 0) const {
109 SubReg,
118 unsigned SubReg = 0) const {
119 return addReg(RegNo, Flags | RegState::Define, SubReg);
125 unsigned SubReg = 0) const {
128 return addReg(RegNo, Flags, SubReg);
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| H A D | TargetRegisterInfo.h | 1088 unsigned SubReg, in shouldCoalesce() argument
1193 unsigned SubReg = 0; variable
1213 unsigned getSubReg() const { return SubReg; } in getSubReg()
1224 SubReg = *Idx++;
1225 if (!SubReg)
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 87 unsigned SubReg; member
98 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
639 if (DefR.SubReg) { in visitPHI()
1084 if (!R.SubReg) { in getCell()
1936 assert(!DefR.SubReg); in evaluate()
2204 if (!R.SubReg) { in evaluate()
2211 if (R.SubReg != Hexagon::isub_lo && R.SubReg != Hexagon::isub_hi) in evaluate()
2296 if (PR.SubReg) in evaluate()
2992 if (R1.SubReg) { in rewriteHexConstUses()
3059 if (SR.SubReg) { in rewriteHexConstUses()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 546 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
547 Reserved.set(SubReg); in getReservedRegs()
553 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
554 Reserved.set(SubReg); in getReservedRegs()
558 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
559 Reserved.set(SubReg); in getReservedRegs()
572 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
573 Reserved.set(SubReg); in getReservedRegs()
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