1533     Register SubReg = e == 1  in buildSpillLoadStore()  local
1596       SubReg = Register(getSubReg(ValueReg,  in buildSpillLoadStore()
1602     unsigned FinalReg = SubReg;  in buildSpillLoadStore()
1615                            .addReg(SubReg, getKillRegState(IsKill));  in buildSpillLoadStore()
1620       SubReg = TmpIntermediateVGPR;  in buildSpillLoadStore()
1637             .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));  in buildSpillLoadStore()
1705         MI->readsRegister(SubReg, this)) {  in buildSpillLoadStore()
1706       MIB.addReg(SubReg, RegState::Implicit);  in buildSpillLoadStore()
1774       Register SubReg =  in spillSGPR()  local
1789                      .addReg(SubReg, getKillRegState(UseKill))  in spillSGPR()
1828         Register SubReg =  in spillSGPR()  local
1836                 .addReg(SubReg, SubKillState)  in spillSGPR()
1890       Register SubReg =  in restoreSGPR()  local
1897                          SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg)  in restoreSGPR()
1923         Register SubReg =  in restoreSGPR()  local
1930                            SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg)  in restoreSGPR()
1970       Register SubReg =  in spillEmergencySGPR()  local
1978               .addReg(SubReg, SubKillState)  in spillEmergencySGPR()
2005       Register SubReg =  in spillEmergencySGPR()  local
2011                          SubReg)  in spillEmergencySGPR()
3020                                     unsigned SubReg,  in shouldCoalesce()  argument
3147 MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,  in findReachingDef()  argument
3159     LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)  in findReachingDef()
3268                                           unsigned SubReg) const {  in getSubRegAlignmentNumBits()
3271     return std::min(128u, getSubRegIdxSize(SubReg));  in getSubRegAlignmentNumBits()
3275     return std::min(32u, getSubRegIdxSize(SubReg));  in getSubRegAlignmentNumBits()