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Searched refs:Src2 (Results 1 – 25 of 47) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp536 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UEQ()
546 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UNE()
555 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_ULE()
564 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UGE()
573 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_ULT()
582 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UGT()
611 Src2.FloatVal == Src2.FloatVal)); in executeFCMP_ORD()
614 Src2.DoubleVal == Src2.DoubleVal)); in executeFCMP_ORD()
642 Src2.FloatVal != Src2.FloatVal)); in executeFCMP_UNO()
645 Src2.DoubleVal != Src2.DoubleVal)); in executeFCMP_UNO()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp135 const MachineOperand &Src2) const;
206 const MachineOperand &Src2) const { in getMuxOpcode()
207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
215 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
301 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
317 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
318 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
H A DHexagonPeephole.cpp152 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
169 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
170 if (Src2.getImm() != 32) in runOnMachineFunction()
H A DHexagonConstPropagation.cpp2601 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2()
2602 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2()
2606 RegisterSubReg R2(Src2); in evaluateHexCompare2()
2609 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2615 RegisterSubReg R2(Src2); in evaluateHexCompare2()
2619 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2633 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexLogical() local
2645 if (!Src2.isImm()) in evaluateHexLogical()
2647 APInt A(32, Src2.getImm(), true); in evaluateHexLogical()
2656 if (!Src2.isImm()) in evaluateHexLogical()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombinerHelper.h31 Register Src1, Register Src2);
33 Register Src1, Register Src2);
H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
48 return FirstMI->definesRegister(Src2->getReg(), TRI); in shouldScheduleAdjacent()
H A DSIShrinkInstructions.cpp400 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma() local
406 if (Src2.isImm() && !TII->isInlineConstant(Src2)) { in shrinkMadFma()
435 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
475 .add(Src2) in shrinkMadFma()
953 const MachineOperand *Src2 = in runOnMachineFunction() local
955 if (!Src2->isReg()) in runOnMachineFunction()
957 Register SReg = Src2->getReg(); in runOnMachineFunction()
981 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction() local
983 if (Src2 && Src2->getReg() != VCCReg) { in runOnMachineFunction()
984 if (Src2->getReg().isVirtual()) in runOnMachineFunction()
[all …]
H A DAMDGPUCombinerHelper.cpp421 Register Src2) { in matchExpandPromotedF16FMed3() argument
428 isFPExtFromF16OrConst(MRI, Src2); in matchExpandPromotedF16FMed3()
434 Register Src2) { in applyExpandPromotedF16FMed3() argument
441 Src2 = Builder.buildFPTrunc(LLT::scalar(16), Src2).getReg(0); in applyExpandPromotedF16FMed3()
446 auto C1 = Builder.buildFMaxNumIEEE(Ty, A1, Src2); in applyExpandPromotedF16FMed3()
H A DGCNDPPCombine.cpp343 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst() local
344 if (Src2) { in createDPPInst()
346 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
351 DPPInst.add(*Src2); in createDPPInst()
397 assert(Src2 && "Expected vop3p with 3 operands"); in createDPPInst()
687 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov() local
690 (Src2 && Src2->isIdenticalTo(*Src0)))) || in combineDPPMov()
692 (Src2 && Src2->isIdenticalTo(*Src1))))) { in combineDPPMov()
H A DAMDGPUInstCombineIntrinsic.cpp46 const APFloat &Src2) { in fmed3AMDGCN() argument
47 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
52 return maxnum(Src1, Src2); in fmed3AMDGCN()
57 return maxnum(Src0, Src2); in fmed3AMDGCN()
769 Value *Src2 = II.getArgOperand(2); in instCombineIntrinsic() local
776 NewCall = IC.Builder.CreateMinNum(Src1, Src2); in instCombineIntrinsic()
778 NewCall = IC.Builder.CreateMinNum(Src0, Src2); in instCombineIntrinsic()
779 } else if (match(Src2, PatternMatch::m_NaN()) || isa<UndefValue>(Src2)) { in instCombineIntrinsic()
799 std::swap(Src1, Src2); in instCombineIntrinsic()
811 II.setArgOperand(2, Src2); in instCombineIntrinsic()
[all …]
H A DSIOptimizeExecMasking.cpp146 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
147 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
162 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
163 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
H A DAMDGPURegBankCombiner.cpp318 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI); in matchFPMed3ToClamp() local
322 if (isFCst(Src1) && !isFCst(Src2)) in matchFPMed3ToClamp()
323 std::swap(Src1, Src2); in matchFPMed3ToClamp()
326 if (!isClampZeroToOne(Src1, Src2)) in matchFPMed3ToClamp()
H A DSIPeepholeSDWA.cpp625 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in matchSDWAOperand() local
626 auto Width = foldToImm(*Src2); in matchSDWAOperand()
1041 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in convertToSDWA() local
1042 assert(Src2); in convertToSDWA()
1043 SDWAInst.add(*Src2); in convertToSDWA()
H A DSIInstrInfo.cpp3486 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
3546 if (Src2->isReg() && Src2->getReg() == Reg) { in FoldImmediate()
3605 Src2->ChangeToImmediate(getImmFor(*Src2)); in FoldImmediate()
3921 .add(*Src2); in convertToThreeAddress()
3976 .add(*Src2) in convertToThreeAddress()
4306 if (Src2) { in canShrink()
4328 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
4400 if (Src2) { in buildShrunkInst()
4403 Inst32.add(*Src2); in buildShrunkInst()
5872 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) { in legalizeOperandsVOP3()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.h39 SDValue Src1, SDValue Src2, SDValue Size,
55 SDValue Src1, SDValue Src2,
H A DSystemZSelectionDAGInfo.cpp174 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
226 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
230 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h730 Src2Ty Src2;
732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
733 : Src0(Src0), Src1(Src1), Src2(Src2) {}
741 Src2.match(MRI, TmpMI->getOperand(3).getReg()));
750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
752 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
759 Src0, Src1, Src2);
H A DMachineIRBuilder.h1100 const SrcOp &Src2, ArrayRef<int> Mask);
1783 const SrcOp &Src1, const SrcOp &Src2,
1785 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1790 const SrcOp &Src1, const SrcOp &Src2,
1792 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
/freebsd-14.2/sys/contrib/edk2/Include/Protocol/
H A DDevicePathUtilities.h69 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp154 MCOperand &Src2, MCOperand &RD, in emitBinary() argument
160 Inst.addOperand(Src2); in emitBinary()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp136 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
143 Inst.addOperand(Src2); in EmitBinary()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp70 Register Src2 = MI.getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd() local
73 auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1429 SDValue Src2 = Node->getOperand(2); in Select() local
1433 if (Src2.getValueType() != XLenVT) in Select()
1436 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1479 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1488 SDValue Src2 = Node->getOperand(3); in Select() local
1492 if (Src2.getValueType() != XLenVT) in Select()
1495 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1571 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1591 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}), in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2193 SDValue Src2 = ShuffleSrc2 ? ShuffleSrc2 : DAG.getUNDEF(VecT); in LowerBUILD_VECTOR() local
2201 if (Src2.getValueType() != VecT) { in LowerBUILD_VECTOR()
2203 Src2.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2206 Src2 = DAG.getBitcast(VecT, Src2); in LowerBUILD_VECTOR()
2223 Result = DAG.getVectorShuffle(VecT, DL, Src1, Src2, MaskRef); in LowerBUILD_VECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp742 const SrcOp &Src2, in buildShuffleVector() argument
746 LLT Src2Ty = Src2.getLLTTy(*getMRI()); in buildShuffleVector()
755 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2}) in buildShuffleVector()

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