3473     MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);  in FoldImmediate()  local
3486       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))  in FoldImmediate()
3497       MachineInstr *Def = MRI->getUniqueVRegDef(Src2->getReg());  in FoldImmediate()
3546     if (Src2->isReg() && Src2->getReg() == Reg) {  in FoldImmediate()
3605       Src2->ChangeToImmediate(getImmFor(*Src2));  in FoldImmediate()
3863   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);  in convertToThreeAddress()  local
3891     if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {  in convertToThreeAddress()
3921                   .add(*Src2);  in convertToThreeAddress()
3942                   .add(*Src2);  in convertToThreeAddress()
3976             .add(*Src2)  in convertToThreeAddress()
4304   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);  in canShrink()  local
4306   if (Src2) {  in canShrink()
4328         if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||  in canShrink()
4398   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);  in buildShrunkInst()  local
4400   if (Src2) {  in buildShrunkInst()
4403       Inst32.add(*Src2);  in buildShrunkInst()
4411       copyFlagsToImplicitVCC(*Inst32, *Src2);  in buildShrunkInst()
4880     const MachineOperand &Src2 = MI.getOperand(Src2Idx);  in verifyInstruction()  local
4881     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {  in verifyInstruction()
4883           !compareMachineOp(Src0, Src2)) {  in verifyInstruction()
5864     MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]);  in legalizeOperandsVOP3()  local
5872     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {  in legalizeOperandsVOP3()
5875         .add(Src2);  in legalizeOperandsVOP3()
5876       Src2.ChangeToRegister(Reg, false);  in legalizeOperandsVOP3()