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Searched refs:RegisterVT (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp50 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs() local
52 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1147 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1191 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1531 MVT RegisterVT; in computeRegisterProperties() local
1534 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1538 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1600 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1614 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1645 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1672 RegisterVT = DestVT; in getVectorTypeBreakdown()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h440 std::optional<MVT> RegisterVT) const override { in getNumRegisters() argument
442 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp109 MVT RegisterVT; in getRegisterTypeForCallingConv() local
111 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
113 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
114 return RegisterVT; in getRegisterTypeForCallingConv()
143 MVT RegisterVT; in getNumRegistersForCallingConv() local
145 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
147 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
173 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
180 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
189 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
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H A DX86ISelLowering.h1532 unsigned &NumIntermediates, MVT &RegisterVT) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp381 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
385 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
H A DSelectionDAGBuilder.cpp352 MVT RegisterVT; in getCopyFromPartsVector() local
359 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
748 MVT RegisterVT; in getCopyToPartsVector() local
754 RegisterVT); in getCopyToPartsVector()
852 MVT RegisterVT = in RegsForValue() local
858 RegVTs.push_back(RegisterVT); in RegsForValue()
881 MVT RegisterVT = isABIMangled() in getCopyFromRegs() local
902 !RegisterVT.isInteger()) in getCopyFromRegs()
964 MVT RegisterVT = isABIMangled() in getCopyToRegs() local
1049 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands() local
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H A DFastISel.cpp1002 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1006 MyFlags.VT = RegisterVT; in lowerCallTo()
H A DSelectionDAG.cpp2436 MVT RegisterVT; in getReducedAlign() local
2439 NumIntermediates, RegisterVT); in getReducedAlign()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1128 MVT &RegisterVT) const;
1135 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
1137 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1652 MVT RegisterVT; in getRegisterType() local
1655 NumIntermediates, RegisterVT); in getRegisterType()
1656 return RegisterVT; in getRegisterType()
1677 std::optional<MVT> RegisterVT = std::nullopt) const {
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1150 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
1158 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1162 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
1163 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
1168 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1176 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1180 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
1182 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1183 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
1184 unsigned NumElements = RegisterVT.getVectorNumElements(); in analyzeFormalArgumentsCompute()
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H A DSIISelLowering.h45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
H A DSIISelLowering.cpp1045 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
1055 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1058 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
1059 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1066 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
1067 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1074 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
1082 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1089 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1090 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h304 unsigned &NumIntermediates, MVT &RegisterVT) const override;
H A DMipsISelLowering.cpp125 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
128 RegisterVT = IntermediateVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
134 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h499 MVT &RegisterVT) const override;
H A DRISCVISelLowering.cpp2203 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2205 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
2210 if (RV64LegalI32 && Subtarget.is64Bit() && RegisterVT == MVT::i32) in getVectorTypeBreakdownForCallingConv()
2211 RegisterVT = MVT::i64; in getVectorTypeBreakdownForCallingConv()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h994 MVT &RegisterVT) const override;
H A DAArch64ISelLowering.cpp27056 MVT RegisterVT; in getRegisterTypeForCallingConv() local
27060 return RegisterVT; in getRegisterTypeForCallingConv()
27082 if (!RegisterVT.isFixedLengthVector() || in getVectorTypeBreakdownForCallingConv()
27083 RegisterVT.getFixedSizeInBits() <= 128) in getVectorTypeBreakdownForCallingConv()
27115 IntermediateVT = RegisterVT = MVT::v16i8; in getVectorTypeBreakdownForCallingConv()
27118 IntermediateVT = RegisterVT = MVT::v8i16; in getVectorTypeBreakdownForCallingConv()
27121 IntermediateVT = RegisterVT = MVT::v4i32; in getVectorTypeBreakdownForCallingConv()
27124 IntermediateVT = RegisterVT = MVT::v2i64; in getVectorTypeBreakdownForCallingConv()
27127 IntermediateVT = RegisterVT = MVT::v8f16; in getVectorTypeBreakdownForCallingConv()
27130 IntermediateVT = RegisterVT = MVT::v4f32; in getVectorTypeBreakdownForCallingConv()
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