| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1481 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
1482 def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
1483 def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
1484 def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
1494 def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
1495 def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
1496 def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
1506 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1507 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1508 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
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| H A D | AArch64ISelDAGToDAG.cpp | 469 template<unsigned RegWidth>
471 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
476 template<unsigned RegWidth>
478 return SelectCVTFixedPosRecipOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosRecipOperand()
3700 unsigned RegWidth, in checkCVTFixedPointOperandWithFBits() argument
3742 if (FBits == 0 || FBits > RegWidth) return false; in checkCVTFixedPointOperandWithFBits()
3749 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
3750 return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, in SelectCVTFixedPosOperand()
3756 unsigned RegWidth) { in SelectCVTFixedPosRecipOperand() argument
3757 return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, in SelectCVTFixedPosRecipOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 831 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias() argument
832 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias()
839 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
840 if (RegWidth == 32) in isMOVZMovAlias()
852 if (isAnyMOVZMovAlias(Value, RegWidth)) in isMOVNMovAlias()
856 if (RegWidth == 32) in isMOVNMovAlias()
859 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
862 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias() argument
863 if (isAnyMOVZMovAlias(Value, RegWidth)) in isAnyMOVWMovAlias()
868 if (RegWidth == 32) in isAnyMOVWMovAlias()
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| H A D | AArch64InstPrinter.cpp | 300 auto PrintMovImm = [&](uint64_t Value, int RegWidth) { in printInst() argument
301 int64_t SExtVal = SignExtend64(Value, RegWidth); in printInst()
324 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
330 PrintMovImm(Value, RegWidth); in printInst()
337 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
340 if (RegWidth == 32) in printInst()
344 PrintMovImm(Value, RegWidth); in printInst()
353 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
355 MI->getOperand(2).getImm(), RegWidth); in printInst()
356 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { in printInst()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 197 unsigned RegWidth = in getMemoryOpCost() local
200 assert(RegWidth && "Non-zero vector register width expected"); in getMemoryOpCost()
202 if (VecWidth % RegWidth == 0) in getMemoryOpCost()
203 return VecWidth / RegWidth; in getMemoryOpCost()
205 const Align RegAlign(RegWidth / 8); in getMemoryOpCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2361 switch (RegWidth) { in getRegClass()
2393 switch (RegWidth) { in getRegClass()
2551 RegWidth = 64; in AddNextRegisterToList()
2556 RegWidth = 64; in AddNextRegisterToList()
2561 RegWidth = 64; in AddNextRegisterToList()
2566 RegWidth = 64; in AddNextRegisterToList()
2571 RegWidth = 64; in AddNextRegisterToList()
2576 RegWidth = 64; in AddNextRegisterToList()
2589 RegWidth += 32; in AddNextRegisterToList()
2761 RegWidth = 32; in ParseSpecialReg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 6178 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6181 RegWidth = 64; in MatchAndEmitInstruction()
6183 RegWidth = 32; in MatchAndEmitInstruction()
6185 if (LSB >= RegWidth) in MatchAndEmitInstruction()
6193 if (RegWidth == 32) in MatchAndEmitInstruction()
6234 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6237 RegWidth = 64; in MatchAndEmitInstruction()
6239 RegWidth = 32; in MatchAndEmitInstruction()
6249 if (RegWidth == 32) in MatchAndEmitInstruction()
6301 RegWidth = 64; in MatchAndEmitInstruction()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1495 TypeSize RegWidth = in getMaximumVF() local
1499 return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth); in getMaximumVF()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1343 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; in buildSpillLoadStore() local
1347 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1348 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore()
1350 unsigned RemSize = RegWidth - Size; in buildSpillLoadStore()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1691 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); variable
1692 return (BitWidth + RegWidth - 1) / RegWidth;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7314 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType() local
7316 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchType()
7325 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchType()
7350 ? NarrowConst.zext(RegWidth) in optimizeSwitchType()
7351 : NarrowConst.sext(RegWidth); in optimizeSwitchType()
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