Lines Matching refs:RegWidth
1270 unsigned RegWidth) { in usesRegister() argument
1273 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1276 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1279 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1348 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1351 unsigned &RegNum, unsigned &RegWidth,
1354 unsigned &RegNum, unsigned &RegWidth,
1357 unsigned &RegWidth,
1360 unsigned &RegWidth,
1363 unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
1366 unsigned RegWidth, SMLoc Loc);
1373 unsigned RegWidth);
2359 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass() argument
2361 switch (RegWidth) { in getRegClass()
2393 switch (RegWidth) { in getRegClass()
2407 switch (RegWidth) { in getRegClass()
2437 switch (RegWidth) { in getRegClass()
2544 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, in AddNextRegisterToList() argument
2551 RegWidth = 64; in AddNextRegisterToList()
2556 RegWidth = 64; in AddNextRegisterToList()
2561 RegWidth = 64; in AddNextRegisterToList()
2566 RegWidth = 64; in AddNextRegisterToList()
2571 RegWidth = 64; in AddNextRegisterToList()
2576 RegWidth = 64; in AddNextRegisterToList()
2585 if (Reg1 != Reg + RegWidth / 32) { in AddNextRegisterToList()
2589 RegWidth += 32; in AddNextRegisterToList()
2669 unsigned SubReg, unsigned RegWidth, in getRegularReg() argument
2677 AlignSize = std::min(llvm::bit_ceil(RegWidth / 32), 4u); in getRegularReg()
2686 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg()
2712 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) { in ParseRegRange() argument
2750 RegWidth = 32 * ((RegHi - RegLo) + 1); in ParseRegRange()
2755 unsigned &RegNum, unsigned &RegWidth, in ParseSpecialReg() argument
2761 RegWidth = 32; in ParseSpecialReg()
2770 unsigned &RegNum, unsigned &RegWidth, in ParseRegularReg() argument
2803 RegWidth = 32; in ParseRegularReg()
2806 if (!ParseRegRange(RegNum, RegWidth)) in ParseRegularReg()
2810 return getRegularReg(RegKind, RegNum, SubReg, RegWidth, Loc); in ParseRegularReg()
2814 unsigned &RegWidth, in ParseRegList() argument
2827 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) in ParseRegList()
2829 if (RegWidth != 32) { in ParseRegList()
2852 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc)) in ParseRegList()
2862 Reg = getRegularReg(RegKind, RegNum, NoSubRegister, RegWidth, ListLoc); in ParseRegList()
2868 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister() argument
2874 Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens); in ParseAMDGPURegister()
2876 Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens); in ParseAMDGPURegister()
2878 Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens); in ParseAMDGPURegister()
2900 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister() argument
2905 if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) { in ParseAMDGPURegister()
2937 unsigned RegWidth) { in updateGprCountSymbols() argument
2947 int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1; in updateGprCountSymbols()
2970 unsigned Reg, RegNum, RegWidth; in parseRegister() local
2972 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) { in parseRegister()
2976 if (!updateGprCountSymbols(RegKind, RegNum, RegWidth)) in parseRegister()
2979 KernelScope.usesRegister(RegKind, RegNum, RegWidth); in parseRegister()