Lines Matching refs:RegWidth
1138 template<int RegWidth, int Shift>
1146 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
1153 template<int RegWidth, int Shift>
1161 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
6178 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6181 RegWidth = 64; in MatchAndEmitInstruction()
6183 RegWidth = 32; in MatchAndEmitInstruction()
6185 if (LSB >= RegWidth) in MatchAndEmitInstruction()
6188 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
6193 if (RegWidth == 32) in MatchAndEmitInstruction()
6209 RegWidth == 32 ? AArch64::WZR : AArch64::XZR, RegKind::Scalar, in MatchAndEmitInstruction()
6234 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6237 RegWidth = 64; in MatchAndEmitInstruction()
6239 RegWidth = 32; in MatchAndEmitInstruction()
6241 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
6244 if (Op4Val < 1 || Op4Val > RegWidth) in MatchAndEmitInstruction()
6249 if (RegWidth == 32) in MatchAndEmitInstruction()
6298 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6301 RegWidth = 64; in MatchAndEmitInstruction()
6303 RegWidth = 32; in MatchAndEmitInstruction()
6305 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
6308 if (Op4Val < 1 || Op4Val > RegWidth) in MatchAndEmitInstruction()
6314 if (NewOp4Val >= RegWidth || NewOp4Val < Op3Val) in MatchAndEmitInstruction()