| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 203 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
204 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
363 const TargetRegisterClass *getRegClass(unsigned RCID) const;
|
| H A D | AMDGPUTargetTransformInfo.h | 120 unsigned getNumberOfRegisters(unsigned RCID) const;
|
| H A D | SIInstrInfo.cpp | 5429 switch (RCID) { in adjustAllocatableRegClass()
5431 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
5434 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
5437 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
5440 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
5443 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
5446 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
5453 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
5499 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local
5509 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
[all …]
|
| H A D | SIRegisterInfo.cpp | 3132 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
3133 switch ((int)RCID) { in getRegClass()
3142 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
|
| H A D | AMDGPUTargetTransformInfo.cpp | 309 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 371 unsigned RCID = N->getConstantOperandVal(0); in getOperandRegClass() local
373 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 929 unsigned RCID; in getRegClassConstraint() local
931 F.hasRegClassConstraint(RCID)) in getRegClassConstraint()
932 return TRI->getRegClass(RCID); in getRegClassConstraint()
1774 unsigned RCID; in print() local
1775 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) { in print()
1777 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1779 OS << ":RC" << RCID; in print()
|
| H A D | TargetInstrInfo.cpp | 1706 unsigned RCID; in createMIROperandComment() local
1707 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) { in createMIROperandComment()
1709 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1711 OS << ":RC" << RCID; in createMIROperandComment()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 754 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
755 if (RCID != -1) { in printRegularOperand()
756 const MCRegisterClass RC = MRI.getRegClass(RCID); in printRegularOperand()
831 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
832 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 2429 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
2430 switch (RCID) { in getRegBitWidth()
2575 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
2576 return getRegBitWidth(RCID) / 8; in getRegOperandSize()
|
| H A D | AMDGPUBaseInfo.h | 1285 unsigned getRegBitWidth(unsigned RCID);
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 269 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline() argument
270 return isRegClass(RCID) || isInlinableImm(type); in isRegOrInline()
273 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
274 return isRegOrInline(RCID, type) || isLiteralImm(type); in isRegOrImmWithInputMods()
412 bool isRegClass(unsigned RCID) const;
416 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
417 return isRegOrInline(RCID, type) && !hasModifiers(); in isRegOrInlineNoMods()
2075 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
2686 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2687 if (RCID == -1) { in getRegularReg()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1594 unsigned RCID; in handleSpecialFP() local
1613 if (F.hasRegClassConstraint(RCID)) { in handleSpecialFP()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 215 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local
217 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
2377 for (const unsigned RCID : in decomposeSubvectorInsertExtractToSubRegs()
2379 if (VecRegClassID > RCID && SubRegClassID <= RCID) { in decomposeSubvectorInsertExtractToSubRegs()
|