269   bool isRegOrInline(unsigned RCID, MVT type) const {  in isRegOrInline()  argument
270     return isRegClass(RCID) || isInlinableImm(type);  in isRegOrInline()
273   bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {  in isRegOrImmWithInputMods()  argument
274     return isRegOrInline(RCID, type) || isLiteralImm(type);  in isRegOrImmWithInputMods()
412   bool isRegClass(unsigned RCID) const;
416   bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {  in isRegOrInlineNoMods()  argument
417     return isRegOrInline(RCID, type) && !hasModifiers();  in isRegOrInlineNoMods()
2075 bool AMDGPUOperand::isRegClass(unsigned RCID) const {  in isRegClass()
2076   return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());  in isRegClass()
2686   int RCID = getRegClass(RegKind, RegWidth);  in getRegularReg()  local
2687   if (RCID == -1) {  in getRegularReg()
2693   const MCRegisterClass RC = TRI->getRegClass(RCID);  in getRegularReg()