Lines Matching refs:RCID
5423 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass() argument
5429 switch (RCID) { in adjustAllocatableRegClass()
5431 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
5434 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
5437 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
5440 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
5443 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
5446 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
5453 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
5499 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local
5500 return adjustAllocatableRegClass(ST, RI, MRI, Desc, RCID, true); in getOpRegClass()
5508 unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass; in legalizeOpWithMove() local
5509 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
8913 const auto RCID = MI.getDesc().operands()[Idx].RegClass; in isBufferSMRD() local
8914 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()