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Searched refs:Order (Results 1 – 25 of 158) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
59 return AO.Order[Pos];
67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos]))
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
92 : Hints(std::move(Hints)), Order(Order), in AllocationOrder()
93 IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {} in AllocationOrder()
102 assert(OrderLimit <= Order.size()); in getOrderLimitEnd()
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
H A DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
49 assert(is_contained(Order, Hints[I]) && in create()
52 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
H A DRegAllocGreedy.cpp400 AllocationOrder &Order, in tryAssign() argument
404 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign()
421 if (Order.isHint(Hint)) { in tryAssign()
536 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit()
580 AllocationOrder &Order, in tryEvict() argument
1157 Cost += calcGlobalSplitCost(Cand, Order); in calculateRegionSplitCostAroundReg()
1179 for (MCPhysReg PhysReg : Order) { in calculateRegionSplitCost()
1659 for (MCPhysReg PhysReg : Order) { in tryLocalSplit()
1833 return tryBlockSplit(VirtReg, Order, NewVRegs); in trySplit()
1991 for (MCRegister PhysReg : Order) { in tryLastChanceRecoloring()
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H A DRegisterClassInfo.cpp134 if (!RCI.Order) in compute()
135 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
160 RCI.Order[N++] = PhysReg; in compute()
172 RCI.Order[N++] = PhysReg; in compute()
192 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
H A DLocalStackSlotAllocation.cpp58 unsigned Order; member in __anon0ab810130111::FrameRef
62 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
65 return std::tie(LocalOffset, FrameIdx, Order) < in operator <()
66 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <()
304 unsigned Order = 0; in insertFrameReferenceRegisters() local
332 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
H A DRegAllocEvictionAdvisor.cpp276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
282 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
294 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
H A DMLRegAllocEvictAdvisor.cpp307 const AllocationOrder &Order,
323 const LiveInterval &VirtReg, const AllocationOrder &Order,
439 const LiveInterval &VirtReg, const AllocationOrder &Order,
664 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
666 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
704 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
778 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidate()
1085 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition() argument
1091 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition()
1094 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition()
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H A DRegAllocGreedy.h331 const AllocationOrder &Order);
351 AllocationOrder &Order,
357 AllocationOrder &Order,
366 AllocationOrder &Order);
370 AllocationOrder &Order, MCRegister PhysReg,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Support/
H A DDynamicLibrary.cpp81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
82 if (Order & SO_LoadOrder) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
97 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
100 if (!Process || (Order & SO_LoadedFirst)) { in Lookup()
101 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
110 if (Order & SO_LoadedLast) { in Lookup()
111 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h748 void setIROrder(unsigned Order) { IROrder = Order; }
1106 IROrder(Order), debugLoc(std::move(dl)) {
1135 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1136 assert(Order >= 0 && "bad IROrder");
1471 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1533 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
2355 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2451 : MemSDNode(NodeTy, Order, DL, VTs, MemVT, MMO) {
2659 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2765 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
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H A DScheduleDAG.h56 Order ///< Any other ordering dependency. enumerator
124 : Dep(S, Order), Contents(), Latency(0) { in SDep()
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
187 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
195 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak()
201 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
207 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster()
473 case Order: in overlaps()
H A DRuntimeLibcalls.h89 AtomicOrdering Order, uint64_t MemSize);
93 Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT);
H A DRegisterClassInfo.h36 std::unique_ptr<MCPhysReg[]> Order; member
41 return ArrayRef(Order.get(), NumRegs);
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h149 unsigned Order; variable
163 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect), in SDDbgValue()
219 unsigned getOrder() const { return Order; } in getOrder()
245 unsigned Order; variable
249 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
259 unsigned getOrder() const { return Order; } in getOrder()
H A DScheduleDAGSDNodes.cpp762 if (Order != 0 && DVOrder != Order) in ProcessSDDbgValues()
787 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
788 if (!Order || Seen.count(Order)) { in ProcessSourceNode()
800 Seen.insert(Order); in ProcessSourceNode()
801 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
806 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
982 unsigned Order = Orders[i].first; in EmitSchedule() local
987 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1005 LastOrder = Order; in EmitSchedule()
1028 unsigned Order = InstrOrder.first; in EmitSchedule() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp251 SmallVector<RegionNode *, 8> Order; member in __anon821ac72d0111::StructurizeCFG
382 if (Order.empty()) in INITIALIZE_PASS_DEPENDENCY()
390 unsigned I = 0, E = Order.size(); in INITIALIZE_PASS_DEPENDENCY()
409 Order[I++] = N.first; in INITIALIZE_PASS_DEPENDENCY()
424 Nodes.insert(Order.begin() + I, Order.begin() + E - 1); in INITIALIZE_PASS_DEPENDENCY()
427 EntryNode.first = Order[E - 1]; in INITIALIZE_PASS_DEPENDENCY()
534 for (RegionNode *RN : reverse(Order)) { in collectInfos()
890 if (!Order.empty() || !ExitUseAllowed) in needPostfix()
977 RegionNode *Node = Order.back(); in handleLoops()
1021 while (!Order.empty()) { in createFlow()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
64 for (MCPhysReg Reg : Order) in addHints()
68 for (MCPhysReg Reg : Order) in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
83 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
126 for (MCPhysReg OrderReg : Order) in getRegAllocationHints()
156 addHints(Order, Hints, RC, MRI); in getRegAllocationHints()
177 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); in getRegAllocationHints()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def147 ArrayRef<PartialMappingIdx> Order) {
148 if (Order.front() != FirstAlias)
150 if (Order.back() != LastAlias)
152 if (Order.front() > Order.back())
155 PartialMappingIdx Previous = Order.front();
157 for (const auto &Current : Order) {
/freebsd-14.2/sys/contrib/device-tree/Bindings/media/
H A Dfsl-vdoa.txt1 Freescale Video Data Order Adapter
4 The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp247 SmallVector<const_iterator, 8> Order; in dump() local
248 Order.reserve(size()); in dump()
250 Order.push_back(I); in dump()
251 llvm::sort(Order, [](const const_iterator &A, const const_iterator &B) { in dump()
254 for (const_iterator I : Order) { in dump()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/
H A DOMPIRBuilder.h222 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo() argument
224 : Flags(Flags), Order(Order), Kind(Kind) {} in OffloadEntryInfo()
228 bool isValid() const { return Order != ~0u; } in isValid()
229 unsigned getOrder() const { return Order; } in getOrder()
248 unsigned Order = ~0u; variable
278 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion() argument
281 : OffloadEntryInfo(OffloadingEntryInfoTargetRegion, Order, Flags), in OffloadEntryInfoTargetRegion()
299 unsigned Order);
364 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar() argument
391 unsigned Order);
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DCodeLayout.cpp1001 std::vector<uint64_t> Order; in concatChains() local
1002 Order.reserve(NumNodes); in concatChains()
1005 Order.push_back(Node->Index); in concatChains()
1006 return Order; in concatChains()
1368 std::vector<uint64_t> Order; in concatChains() local
1369 Order.reserve(NumNodes); in concatChains()
1372 Order.push_back(Node->Index); in concatChains()
1373 return Order; in concatChains()
1435 Addr[Order[Idx]] = Addr[Order[Idx - 1]] + NodeSizes[Order[Idx - 1]]; in calcExtTspScore()
1454 std::vector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
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/freebsd-14.2/contrib/libxo/tests/core/saved/
H A Dtest_01.T.out11 Item Total Sold In Stock On Order SKU
54 Item Total Sold In Stock On Order SKU
/freebsd-14.2/contrib/llvm-project/llvm/lib/Bitcode/Writer/
H A DValueEnumerator.cpp796 SmallVector<MDIndex, 64> Order; in organizeMetadata() local
797 Order.reserve(MetadataMap.size()); in organizeMetadata()
799 Order.push_back(MetadataMap.lookup(MD)); in organizeMetadata()
807 llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) { in organizeMetadata()
817 for (unsigned I = 0, E = Order.size(); I != E && !Order[I].F; ++I) { in organizeMetadata()
818 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
826 if (MDs.size() == Order.size()) in organizeMetadata()
833 for (unsigned I = MDs.size(), E = Order.size(), ID = MDs.size(); I != E; in organizeMetadata()
835 unsigned F = Order[I].F; in organizeMetadata()
847 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/DirectX/DXILWriter/
H A DDXILValueEnumerator.cpp801 SmallVector<MDIndex, 64> Order; in organizeMetadata() local
802 Order.reserve(MetadataMap.size()); in organizeMetadata()
804 Order.push_back(MetadataMap.lookup(MD)); in organizeMetadata()
812 llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) { in organizeMetadata()
822 for (unsigned I = 0, E = Order.size(); I != E && !Order[I].F; ++I) { in organizeMetadata()
823 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
831 if (MDs.size() == Order.size()) in organizeMetadata()
838 for (unsigned I = MDs.size(), E = Order.size(), ID = MDs.size(); I != E; in organizeMetadata()
840 unsigned F = Order[I].F; in organizeMetadata()
852 auto *MD = Order[I].get(OldMDs); in organizeMetadata()

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