1*0b57cec5SDimitry Andric //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric //
9*0b57cec5SDimitry Andric // This file implements an allocation order for virtual registers.
10*0b57cec5SDimitry Andric //
11*0b57cec5SDimitry Andric // The preferred allocation order for a virtual register depends on allocation
12*0b57cec5SDimitry Andric // hints and target hooks. The AllocationOrder class encapsulates all of that.
13*0b57cec5SDimitry Andric //
14*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
15*0b57cec5SDimitry Andric 
16*0b57cec5SDimitry Andric #include "AllocationOrder.h"
17*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
18*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
19*0b57cec5SDimitry Andric #include "llvm/CodeGen/RegisterClassInfo.h"
20*0b57cec5SDimitry Andric #include "llvm/CodeGen/VirtRegMap.h"
21*0b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
22*0b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
23*0b57cec5SDimitry Andric 
24*0b57cec5SDimitry Andric using namespace llvm;
25*0b57cec5SDimitry Andric 
26*0b57cec5SDimitry Andric #define DEBUG_TYPE "regalloc"
27*0b57cec5SDimitry Andric 
28*0b57cec5SDimitry Andric // Compare VirtRegMap::getRegAllocPref().
create(unsigned VirtReg,const VirtRegMap & VRM,const RegisterClassInfo & RegClassInfo,const LiveRegMatrix * Matrix)29*0b57cec5SDimitry Andric AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
30*0b57cec5SDimitry Andric                                         const RegisterClassInfo &RegClassInfo,
31*0b57cec5SDimitry Andric                                         const LiveRegMatrix *Matrix) {
32*0b57cec5SDimitry Andric   const MachineFunction &MF = VRM.getMachineFunction();
33*0b57cec5SDimitry Andric   const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
34*0b57cec5SDimitry Andric   auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
35*0b57cec5SDimitry Andric   SmallVector<MCPhysReg, 16> Hints;
36*0b57cec5SDimitry Andric   bool HardHints =
37*0b57cec5SDimitry Andric       TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
38*0b57cec5SDimitry Andric 
39*0b57cec5SDimitry Andric   LLVM_DEBUG({
40*0b57cec5SDimitry Andric     if (!Hints.empty()) {
41*0b57cec5SDimitry Andric       dbgs() << "hints:";
42*0b57cec5SDimitry Andric       for (unsigned I = 0, E = Hints.size(); I != E; ++I)
43*0b57cec5SDimitry Andric         dbgs() << ' ' << printReg(Hints[I], TRI);
44*0b57cec5SDimitry Andric       dbgs() << '\n';
45*0b57cec5SDimitry Andric     }
46*0b57cec5SDimitry Andric   });
47*0b57cec5SDimitry Andric #ifndef NDEBUG
48*0b57cec5SDimitry Andric   for (unsigned I = 0, E = Hints.size(); I != E; ++I)
49*0b57cec5SDimitry Andric     assert(is_contained(Order, Hints[I]) &&
50*0b57cec5SDimitry Andric            "Target hint is outside allocation order.");
51*0b57cec5SDimitry Andric #endif
52*0b57cec5SDimitry Andric   return AllocationOrder(std::move(Hints), Order, HardHints);
53*0b57cec5SDimitry Andric }
54*0b57cec5SDimitry Andric