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Searched refs:ItinData (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
41 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
44 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
45 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
73 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
113 if (!ItinData || ItinData->isEmpty()) in getHazardType()
128 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
129 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
172 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
187 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction()
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H A DTargetInstrInfo.cpp1382 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1385 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1393 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1400 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1415 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1419 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
1449 if (!ItinData) in getInstrLatency()
1452 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1459 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
1464 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h316 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
319 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
426 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
430 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
434 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
438 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
442 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
450 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
457 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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H A DARMBaseInstrInfo.cpp3764 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3769 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3772 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
4366 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
4468 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
4763 if (!ItinData) in getInstrLatency()
4769 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) in getInstrLatency()
4770 return getNumMicroOps(ItinData, MI); in getInstrLatency()
4790 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
4828 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument
36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()
H A DPPCInstrInfo.h320 unsigned getInstrLatency(const InstrItineraryData *ItinData,
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
329 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
333 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
H A DPPCInstrInfo.cpp138 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
141 if (!ItinData || UseOldLatencyCalc) in getInstrLatency()
142 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
158 std::optional<unsigned> Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency()
169 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
172 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
193 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp93 Record *ItinData, std::string &ItinString,
98 Record *ItinData,
343 Record *ItinData, in FormItineraryStageString() argument
347 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
390 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
403 Record *ItinData, in FormItineraryBypassString() argument
406 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
505 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
510 if (ItinData) in EmitStageAndOperandCycleData()
518 if (ItinData) { in EmitStageAndOperandCycleData()
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H A DCodeGenSchedule.cpp1186 for (Record *ItinData : ItinRecords) { in collectProcItins()
1187 const Record *ItinDef = ItinData->getValueAsDef("TheClass"); in collectProcItins()
1194 ProcModel.ItinDefList[SC.Index] = ItinData; in collectProcItins()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h280 unsigned getInstrLatency(const InstrItineraryData *ItinData,
312 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
460 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
H A DHexagonInstrInfo.cpp1969 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1972 return getInstrTimingClassLatency(ItinData, MI); in getInstrLatency()
4279 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument
4282 if (!ItinData) in getInstrTimingClassLatency()
4283 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
4287 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4299 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
4330 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h95 const InstrItineraryData *ItinData; variable
H A DTargetInstrInfo.h1722 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1734 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode,
1746 getOperandLatency(const InstrItineraryData *ItinData,
1753 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1759 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h207 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
H A DSIInstrInfo.h1350 unsigned getInstrLatency(const InstrItineraryData *ItinData,
H A DR600InstrInfo.cpp983 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
H A DSIInstrInfo.cpp9410 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument