Lines Matching refs:ItinData

1382 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
1385 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1393 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1395 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1398 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1400 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1406 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1413 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1415 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1419 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
1444 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1449 if (!ItinData) in getInstrLatency()
1452 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1458 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); in hasLowDefLatency() local
1459 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
1464 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1584 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
1588 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()