3460 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,  in getNumMicroOpsSwiftLdSt()  argument
3465     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());  in getNumMicroOpsSwiftLdSt()
3762 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()  argument
3764   if (!ItinData || ItinData->isEmpty())  in getNumMicroOps()
3769   int ItinUOps = ItinData->getNumMicroOps(Class);  in getNumMicroOps()
3772       return getNumMicroOpsSwiftLdSt(ItinData, MI);  in getNumMicroOps()
3876 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()  argument
3882     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3916 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()  argument
3922     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
3950 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()  argument
3955     return ItinData->getOperandCycle(UseClass, UseIdx);  in getVSTMUseCycle()
3989 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()  argument
3994     return ItinData->getOperandCycle(UseClass, UseIdx);  in getSTMUseCycle()
4017     const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID,  in getOperandLatency()  argument
4024     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
4033     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
4042     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4063     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4074     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);  in getOperandLatency()
4083     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
4101     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
4117       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,  in getOperandLatency()
4120     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
4363     const InstrItineraryData *ItinData, const MachineInstr &DefMI,  in getOperandLatency()  argument
4366   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
4392       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,  in getOperandLatency()
4397     const InstrItineraryData *ItinData, const MachineInstr &DefMI,  in getOperandLatencyImpl()  argument
4412     unsigned Latency = getInstrLatency(ItinData, DefMI);  in getOperandLatencyImpl()
4439       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);  in getOperandLatencyImpl()
4457 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
4468   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
4473         ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
4489       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);  in getOperandLatency()
4734 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4749         Latency += getInstrLatency(ItinData, *I, PredCost);  in getInstrLatency()
4763   if (!ItinData)  in getInstrLatency()
4769   if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)  in getInstrLatency()
4770     return getNumMicroOps(ItinData, MI);  in getInstrLatency()
4773   unsigned Latency = ItinData->getStageLatency(Class);  in getInstrLatency()
4785 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4790   if (!ItinData || ItinData->isEmpty())  in getInstrLatency()
4796     return ItinData->getStageLatency(get(Opcode).getSchedClass());  in getInstrLatency()
4827   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();  in hasLowDefLatency()  local
4828   if (!ItinData || ItinData->isEmpty())  in hasLowDefLatency()
4835         ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()