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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td61 bits<16> Inst;
75 bits<16> Inst;
87 bits<16> Inst;
100 bits<16> Inst;
114 bits<16> Inst;
127 bits<16> Inst;
139 bits<16> Inst;
150 bits<16> Inst;
161 bits<16> Inst;
172 bits<16> Inst;
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H A DMicroMips32r6InstrFormats.td40 bits<16> Inst;
50 bits<16> Inst;
60 bits<16> Inst;
72 bits<32> Inst;
85 bits<32> Inst;
96 bits<16> Inst;
107 bits<16> Inst;
119 bits<32> Inst;
133 bits<32> Inst;
147 bits<32> Inst;
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H A DMipsMSAInstrFormats.td37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
50 let Inst{19-16} = m;
52 let Inst{10-6} = wd;
63 let Inst{20-16} = m;
65 let Inst{10-6} = wd;
75 let Inst{22} = 0b0;
76 let Inst{21-16} = m;
120 let Inst{16} = df;
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H A DMipsInstrFormats.td179 bits<32> Inst;
193 bits<32> Inst;
208 bits<32> Inst;
221 bits<32> Inst;
236 bits<32> Inst;
249 bits<32> Inst;
265 bits<32> Inst;
281 bits<32> Inst;
293 bits<32> Inst;
306 bits<32> Inst;
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H A DMicroMipsDSPInstrFormats.td30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
53 let Inst{25-21} = rt;
54 let Inst{20-16} = rs;
55 let Inst{15-14} = ac;
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H A DMips32r6InstrFormats.td181 bits<32> Inst;
196 bits<32> Inst;
207 bits<32> Inst;
223 bits<32> Inst;
238 bits<32> Inst;
252 bits<32> Inst;
264 bits<32> Inst;
276 bits<32> Inst;
288 bits<32> Inst;
300 bits<32> Inst;
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H A DMipsDSPInstrFormats.td72 let Inst{25-21} = rs;
73 let Inst{20-16} = rt;
74 let Inst{15-11} = rd;
75 let Inst{10-6} = op;
85 let Inst{25-21} = rs;
86 let Inst{20-16} = 0;
87 let Inst{15-11} = rd;
101 let Inst{15-11} = 0;
141 let Inst{25-21} = 0;
263 let Inst{10-6} = 0;
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H A DMipsMTInstrFormats.td40 bits<32> Inst;
45 let Inst{20-16} = rt;
54 bits<32> Inst;
63 let Inst{20-16} = rt;
64 let Inst{15-11} = rd;
66 let Inst{5} = u;
67 let Inst{4} = h;
73 bits<32> Inst;
79 let Inst{25-21} = rs;
80 let Inst{20-16} = rt;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td13 let Inst{12-8} = Vu32{4-0};
17 let Inst{4-0} = Vdd32{4-0};
21 let Inst{11-5} = Ii{6-0};
25 let Inst{1-0} = Pd4{1-0};
33 let Inst{1-0} = Pd4{1-0};
38 let Inst{7-1} = Ii{8-2};
45 let Inst{8-8} = n1{0-0};
58 let Inst{7-7} = Ii{0-0};
61 let Inst{6-5} = II{1-0};
75 let Inst{6-3} = Ii{4-1};
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp262 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
265 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
268 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
271 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
274 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
277 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
280 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
283 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
310 Inst.setOpcode(XCore::LSS_3r); in Decode2OpInstructionFail()
313 Inst.setOpcode(XCore::LSU_3r); in Decode2OpInstructionFail()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp739 Inst.addOperand( in DecodeMatrixTile()
918 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4)) in DecodePCRelLabel19()
1059 switch (Inst.getOpcode()) { in DecodeThreeAddrSRegInstruction()
1119 switch (Inst.getOpcode()) { in DecodeMoveImmInstruction()
1138 Inst.addOperand(Inst.getOperand(0)); in DecodeMoveImmInstruction()
1152 switch (Inst.getOpcode()) { in DecodeUnsignedLdStInstruction()
1217 switch (Inst.getOpcode()) { in DecodeSignedLdStInstruction()
1270 switch (Inst.getOpcode()) { in DecodeSignedLdStInstruction()
1628 switch (Inst.getOpcode()) { in DecodeAuthLoadInstruction()
1664 switch (Inst.getOpcode()) { in DecodeAddSubERegInstruction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
32 let Inst{11-7} = rs1;
33 let Inst{6-2} = rs2;
48 let Inst{11-7} = rd;
63 let Inst{6-2} = rs2;
74 let Inst{4-2} = rd;
80 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
88 let Inst{9-7} = rs1;
89 let Inst{4-2} = rd;
95 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
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H A DRISCVInstrFormatsV.td63 let Inst{31} = 1;
64 let Inst{30} = 1;
68 let Inst{11-7} = rd;
80 let Inst{31} = 0;
96 let Inst{31} = 1;
116 let Inst{25} = vm;
136 let Inst{25} = vm;
155 let Inst{25} = vm;
175 let Inst{25} = vm;
194 let Inst{25} = vm;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td13 let Inst{15} = 0;
14 let Inst{14 - 10} = sop;
22 let Inst{15} = 0;
34 let Inst{10 - 8} = rx;
35 let Inst{7 - 5} = rz;
36 let Inst{4 - 2} = ry;
37 let Inst{1, 0} = sop;
47 let Inst{9 - 6} = rz;
48 let Inst{5 - 2} = rx;
49 let Inst{1, 0} = sop;
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H A DCSKYInstrFormats.td45 field bits<32> Inst;
51 field bits<16> Inst;
138 let Inst{15 - 0} = 0;
151 let Inst{15 - 2} = 0;
161 let Inst{15 - 0} = 0;
318 let Inst{4 - 0} = 0;
319 let Inst{25} = S;
320 let Inst{21} = I;
331 let Inst{4 - 0} = 0;
350 let Inst{15} = 1;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td15 field bits<32> Inst;
22 let Inst{0-5} = opcode;
92 field bits<64> Inst;
585 let Inst{6} = 0;
590 let Inst{31} = 0;
631 let Inst{15} = L;
1311 let Inst{11} = S;
1780 let Inst{6} = 0;
1782 let Inst{15} = 0;
2280 let Inst{15} = R;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp200 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
206 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
212 return decodeUImmOperand<3>(Inst, Imm); in decodeU3ImmOperand()
218 return decodeUImmOperand<4>(Inst, Imm); in decodeU4ImmOperand()
224 return decodeUImmOperand<8>(Inst, Imm); in decodeU8ImmOperand()
230 return decodeUImmOperand<12>(Inst, Imm); in decodeU12ImmOperand()
236 return decodeUImmOperand<16>(Inst, Imm); in decodeU16ImmOperand()
242 return decodeUImmOperand<32>(Inst, Imm); in decodeU32ImmOperand()
248 return decodeSImmOperand<8>(Inst, Imm); in decodeS8ImmOperand()
354 uint64_t Inst = 0; in getInstruction() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
95 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
107 return decodeRegisterClass(Inst, RegNo, FRegs); in DecodeF4RCRegisterClass()
113 return decodeRegisterClass(Inst, RegNo, FRegs); in DecodeF8RCRegisterClass()
133 return decodeRegisterClass(Inst, RegNo, VRegs); in DecodeVRRCRegisterClass()
157 return decodeRegisterClass(Inst, RegNo, RRegs); in DecodeGPRCRegisterClass()
169 return decodeRegisterClass(Inst, RegNo, XRegs); in DecodeG8RCRegisterClass()
253 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
272 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand()
302 Inst.addOperand(MCOperand::createImm(Disp)); in decodeDispRIHashOperand()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td27 let Inst{31-0} = op;
29 let Inst{4-0} = xd;
40 let Inst{31-0} = op;
41 let Inst{9-5} = xj;
42 let Inst{4-0} = xd;
53 let Inst{9-5} = rj;
54 let Inst{4-0} = xd;
65 let Inst{9-5} = xj;
66 let Inst{2-0} = cd;
80 let Inst{9-5} = xj;
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H A DLoongArchLSXInstrFormats.td27 let Inst{31-0} = op;
29 let Inst{4-0} = vd;
40 let Inst{31-0} = op;
41 let Inst{9-5} = vj;
42 let Inst{4-0} = vd;
53 let Inst{9-5} = rj;
54 let Inst{4-0} = vd;
65 let Inst{9-5} = vj;
66 let Inst{2-0} = cd;
80 let Inst{9-5} = vj;
[all …]
H A DLoongArchInstrFormats.td22 field bits<32> Inst;
57 let Inst{31-0} = op;
58 let Inst{9-5} = rj;
59 let Inst{4-0} = rd;
73 let Inst{9-5} = rj;
74 let Inst{4-0} = rd;
90 let Inst{9-5} = rj;
91 let Inst{4-0} = rd;
107 let Inst{9-5} = rj;
108 let Inst{4-0} = rd;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1741 switch (Inst.getOpcode()) { in DecodeRegListOperand()
1874 switch (Inst.getOpcode()) { in DecodeCopMemInstruction()
1951 switch (Inst.getOpcode()) { in DecodeCopMemInstruction()
2012 switch (Inst.getOpcode()) { in DecodeCopMemInstruction()
2054 switch (Inst.getOpcode()) { in DecodeAddrMode2IdxInstruction()
2192 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) in DecodeTSBInstruction()
2520 Inst.addOperand( in DecodeMemMultipleWritebackInstruction()
2672 Inst.setOpcode(Opcode); in DecodeT2HintSpaceInstruction()
3037 switch(Inst.getOpcode()) { in DecodeVLDInstruction()
3943 switch(Inst.getOpcode()) { in DecodeThumbAddSpecialReg()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td32 field bits<24> Inst;
40 field bits<16> Inst;
55 let Inst{11-8} = s;
56 let Inst{7-4} = t;
72 let Inst{7-4} = t;
87 let Inst{7-4} = t;
98 let Inst{7-4} = t;
111 let Inst{7-4} = t;
194 let Inst{7} = i;
207 let Inst{7} = i;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp67 MAI->addInitialFrameState(Inst); in createRISCVMCAsmInfo()
167 if (isTerminator(Inst) || isCall(Inst)) { in updateState()
172 switch (Inst.getOpcode()) { in updateState()
203 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { in evaluateBranch()
229 switch (Inst.getOpcode()) { in isTerminator()
242 switch (Inst.getOpcode()) { in isCall()
255 switch (Inst.getOpcode()) { in isReturn()
270 return isBranchImpl(Inst); in isBranch()
277 return isBranchImpl(Inst); in isUnconditionalBranch()
284 switch (Inst.getOpcode()) { in isIndirectBranch()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td14 field bits<64> Inst;
162 let Inst{5} = N;
181 let Inst{4} = 0;
203 let Inst{17} = 1;
211 let Inst{17} = 0;
232 let Inst{16} = 1;
236 let Inst{5} = N;
238 let Inst{3} = 0;
305 let Inst{5} = 0;
349 let Inst{5} = 1;
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