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Searched refs:GPR64RegClass (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
67 const MCRegisterClass *GPR64RegClass; variable
H A DMipsMachineFunction.cpp50 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
82 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
162 ? Mips::GPR64RegClass in createEhDataRegsFI()
H A DMipsSERegisterInfo.cpp59 return &Mips::GPR64RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()
226 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
304 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
598 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsSEFrameLowering.cpp422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
896 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
912 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSubtarget.cpp233 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
H A DMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsSEISelLowering.cpp70 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
3326 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3512 : &Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3518 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3564 : &Mips::GPR64RegClass); in emitLD_F16_PSEUDO()
3656 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
3760 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPEXTEND_PSEUDO()
H A DMipsISelLowering.cpp4143 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4167 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4831 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitLDR_D()
4966 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitSTR_D()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp108 const MCRegisterClass *GPR64RegClass = in hasLiveDefs() local
119 RegIsGPR64 = GPR64RegClass->contains(MO.getReg()); in hasLiveDefs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp414 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
475 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
1733 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()
1835 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1849 RC = &AArch64::GPR64RegClass; in emitLoad()
2688 RC = &AArch64::GPR64RegClass; in selectSelect()
2980 RC = &AArch64::GPR64RegClass; in fastLowerArguments()
3247 CallReg = createResultReg(&AArch64::GPR64RegClass); in fastLowerCall()
4820 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast()
4913 RC = &AArch64::GPR64RegClass; in selectSDiv()
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H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
110 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
H A DAArch64CleanupLocalDynamicTLSPass.cpp126 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
H A DAArch64FrameLowering.cpp347 if (AArch64::GPR64RegClass.contains(Reg)) in homogeneousPrologEpilog()
536 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateCallFramePseudoInstr()
1033 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()
2824 if (AArch64::GPR64RegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()
2843 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
3261 const bool RegIsGPR64 = AArch64::GPR64RegClass.contains(Reg); in determineCalleeSaves()
3276 if (RegIsGPR64 && !AArch64::GPR64RegClass.contains(PairedReg)) { in determineCalleeSaves()
3281 AArch64::GPR64RegClass.contains(Reg, PairedReg) || in determineCalleeSaves()
3286 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves()
3300 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves()
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H A DAArch64RegisterInfo.cpp526 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()
833 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in createScratchRegisterForInstruction()
925 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
H A DAArch64InstrInfo.cpp835 RC = &AArch64::GPR64RegClass; in insertSelect()
4692 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()
4697 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
5332 &AArch64::GPR64RegClass); in emitFrameOffsetAdj()
6964 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
6979 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
7005 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
7065 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
7089 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
7115 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
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H A DAArch64CollectLOH.cpp502 for (MCPhysReg Reg : AArch64::GPR64RegClass) in handleNormalInst()
H A DAArch64FalkorHWPFFix.cpp749 for (unsigned ScratchReg : AArch64::GPR64RegClass) { in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp1199 LdRt, AArch64::sub_32, &AArch64::GPR64RegClass)) in promoteLoadFromStore()
H A DAArch64ISelLowering.cpp6723 RC = &AArch64::GPR64RegClass; in LowerFormalArguments()
6812 Register VReg = MF.addLiveIn(AArch64::X4, &AArch64::GPR64RegClass); in LowerFormalArguments()
6978 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in LowerFormalArguments()
7076 Register VReg = MF.addLiveIn(AArch64::X4, &AArch64::GPR64RegClass); in saveVarArgRegisters()
7085 Register VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters()
7489 AArch64::GPR64RegClass.contains(MO.getReg()))) in AdjustInstrPostInstrSelection()
8344 if (AArch64::GPR64RegClass.contains(*I)) in LowerReturn()
9932 Register VReg = MF.addLiveIn(AArch64::X4, &AArch64::GPR64RegClass); in LowerWin64_VASTART()
10217 Register Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); in LowerRETURNADDR()
25434 if (AArch64::GPR64RegClass.contains(*I)) in insertCopiesSplitCSR()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp570 : &AArch64::GPR64RegClass; in getRegClassForTypeOnBank()
608 : &AArch64::GPR64RegClass; in getMinClassForRegBank()
2072 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI); in preISelLower()
2099 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
3209 SrcRC == &AArch64::GPR64RegClass) { in select()
3381 {&AArch64::GPR64RegClass}, {}) in select()
3607 IsSet ? AArch64::GPR64RegClass : AArch64::GPR64commonRegClass; in selectMOPS()
3612 RBI.constrainGenericRegister(SizeCopy, AArch64::GPR64RegClass, MRI); in selectMOPS()
3976 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues()
5374 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in selectUSMovFromExtend()
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H A DAArch64LegalizerInfo.cpp1334 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1356 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1924 auto Scratch = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp513 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in handleMustTailForwardedRegisters()