381   const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass  in materializeInt()
414         &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in materializeFP()
475       ResultReg = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
488     Register Result64 = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
1319       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rr()
1362     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_ri()
1405       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rs()
1447     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rx()
1733     RC = &AArch64::GPR64RegClass;  in emitLogicalOp_rs()
1835              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1840              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1845              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1849     RC = &AArch64::GPR64RegClass;  in emitLoad()
1877     Register Reg64 = createResultReg(&AArch64::GPR64RegClass);  in emitLoad()
2688     RC = &AArch64::GPR64RegClass;  in selectSelect()
2847       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2980       RC = &AArch64::GPR64RegClass;  in fastLowerArguments()
3247       CallReg = createResultReg(&AArch64::GPR64RegClass);  in fastLowerCall()
3440     Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in fastLowerIntrinsicCall()
3451       DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,  in fastLowerIntrinsicCall()
4014       Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emiti1Ext()
4047       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitMul_rr()
4055   return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,  in emitSMULL_rr()
4063   return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,  in emitUMULL_rr()
4081       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_rr()
4106       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_ri()
4183       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_rr()
4209       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_ri()
4299       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_rr()
4325       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_ri()
4437     Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emitIntExt()
4447       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4534     Register Reg64 = createResultReg(&AArch64::GPR64RegClass);  in optimizeIntExtLoad()
4577         Register ResultReg = createResultReg(&AArch64::GPR64RegClass);  in selectIntExt()
4630       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()
4820   case MVT::i64: RC = &AArch64::GPR64RegClass; break;  in selectBitCast()
4913     RC = &AArch64::GPR64RegClass;  in selectSDiv()
5052     ResRC = &AArch64::GPR64RegClass;  in selectAtomicCmpXchg()