Home
last modified time | relevance | path

Searched refs:FPU (Results 1 – 25 of 76) sorted by relevance

1234

/freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/
H A DAArch64.cpp63 FPU |= NeonMode; in setArchFeatures()
91 FPU |= NeonMode; in setArchFeatures()
109 FPU |= SveMode; in setArchFeatures()
122 FPU |= NeonMode; in setArchFeatures()
395 if (FPU & FPUMode) in getTargetDefines()
417 if (FPU & SveMode) in getTargetDefines()
420 if ((FPU & NeonMode) && (FPU & SveMode)) in getTargetDefines()
612 if (FPU & SveMode) in getTargetDefines()
1005 FPU &= ~FPUMode; in handleTargetFeatures()
1007 FPU &= ~SveMode; in handleTargetFeatures()
[all …]
H A DARM.cpp505 FPU = 0; in handleTargetFeatures()
532 FPU |= VFP2FPU; in handleTargetFeatures()
538 FPU |= VFP3FPU; in handleTargetFeatures()
544 FPU |= VFP4FPU; in handleTargetFeatures()
550 FPU |= FPARMV8; in handleTargetFeatures()
555 FPU |= NeonFPU; in handleTargetFeatures()
590 FPU |= FPARMV8; in handleTargetFeatures()
937 if (FPU & VFP2FPU) in getTargetDefines()
939 if (FPU & VFP3FPU) in getTargetDefines()
941 if (FPU & VFP4FPU) in getTargetDefines()
[all …]
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DLoongArch.cpp39 int FPU = -1; in getLoongArchABI() local
43 FPU = 64; in getLoongArchABI()
45 FPU = 32; in getLoongArchABI()
47 FPU = 0; in getLoongArchABI()
80 if (FPU != -1 && ImpliedFPU != FPU) in getLoongArchABI()
92 switch (FPU) { in getLoongArchABI()
153 StringRef FPU = A->getValue(); in getLoongArchTargetFeatures() local
154 if (FPU == "64") { in getLoongArchTargetFeatures()
157 } else if (FPU == "32") { in getLoongArchTargetFeatures()
160 } else if (FPU == "0" || FPU == "none") { in getLoongArchTargetFeatures()
[all …]
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfoPOSIX_arm.cpp25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::FPU, fpscr) + \
29 sizeof(RegisterInfoPOSIX_arm::FPU))
32 sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
43 (sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
163 return sizeof(struct RegisterInfoPOSIX_arm::FPU); in GetFPRSize()
H A DRegisterContextDarwin_arm64.h80 struct FPU { struct
114 FPUWordCount = sizeof(FPU) / sizeof(uint32_t), // ARM_NEON_STATE64_COUNT
123 FPU fpu;
204 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
212 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextDarwin_i386.h75 struct FPU { struct
107 FPUWordCount = sizeof(FPU) / sizeof(uint32_t), argument
114 FPU fpu;
185 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
191 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextDarwin_x86_64.h80 struct FPU { struct
112 FPUWordCount = sizeof(FPU) / sizeof(uint32_t), argument
119 FPU fpu;
190 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
196 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextMach_i386.cpp29 int RegisterContextMach_i386::DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) { in DoReadFPU()
47 const FPU &fpu) { in DoWriteFPU()
49 tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)), in DoWriteFPU()
H A DRegisterContextMach_x86_64.cpp31 FPU &fpu) { in DoReadFPU()
50 const FPU &fpu) { in DoWriteFPU()
52 tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)), in DoWriteFPU()
H A DRegisterContextDarwin_arm.h98 struct FPU { struct
148 FPUWordCount = sizeof(FPU) / sizeof(uint32_t),
156 FPU fpu;
237 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
245 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextMach_arm.cpp31 int RegisterContextMach_arm::DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) { in DoReadFPU()
54 const FPU &fpu) { in DoWriteFPU()
56 tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)), in DoWriteFPU()
H A DRegisterContextMach_i386.h24 int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override;
30 int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override;
H A DRegisterContextMach_x86_64.h25 int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override;
31 int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override;
H A DRegisterContextMach_arm.h24 int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override;
32 int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override;
H A DRegisterInfoPOSIX_arm64.cpp25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
49 sizeof(RegisterInfoPOSIX_arm64::FPU))
53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
285 return sizeof(struct RegisterInfoPOSIX_arm64::FPU); in GetFPRSize()
H A DRegisterContextDarwin_i386.cpp133 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::FPU, reg) + \
138 sizeof(RegisterContextDarwin_i386::FPU))
148 #reg, NULL, sizeof(((RegisterContextDarwin_i386::FPU *) NULL)->reg), \
152 sizeof(((RegisterContextDarwin_i386::FPU *) NULL)->reg[i].bytes), \
164 sizeof(RegisterContextDarwin_i386::FPU) + \
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td83 def : WriteRes<FPU, [Z196_FPUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
748 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
760 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
764 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
803 def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
832 def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr],
870 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEXR$")>;
884 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
901 def : InstRW<[WLat7, FPU, NormalGr], (instregex "H(E|D)R$")>;
[all …]
H A DSystemZScheduleZEC12.td84 def : WriteRes<FPU, [ZEC12_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
786 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
798 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
802 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
841 def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
870 def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr],
908 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEXR$")>;
922 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
939 def : InstRW<[WLat7, FPU, NormalGr], (instregex "H(E|D)R$")>;
[all …]
/freebsd-14.2/sys/contrib/openzfs/config/
H A Dkernel-fpu.m42 dnl # Handle differences in kernel FPU code.
11 dnl # 5.0: Wrappers have been introduced to save/restore the FPU state.
100 [kernel exports FPU functions])
112 [kernel exports FPU functions])
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMELFStreamer.cpp97 void emitFPU(ARM::FPUKind FPU) override;
252 void ARMTargetAsmStreamer::emitFPU(ARM::FPUKind FPU) { in emitFPU() argument
253 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
386 ARM::FPUKind FPU = ARM::FK_INVALID; member in __anon42dabcca0111::ARMTargetELFStreamer
418 void emitFPU(ARM::FPUKind FPU) override;
933 void ARMTargetELFStreamer::emitFPU(ARM::FPUKind Value) { FPU = Value; } in emitFPU()
938 switch (FPU) { in emitFPUDefaultAttributes()
1045 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
1053 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
1083 FPU = ARM::FK_INVALID; in finishAttributeSection()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68k.td42 "Is M68881 (FPU) ISA supported">;
46 "Is M68882 (FPU) ISA supported",
/freebsd-14.2/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp219 ARM::FPUKind ARM::parseFPU(StringRef FPU) { in parseFPU() argument
220 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
234 StringRef ARM::getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
235 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
248 .Default(FPU); in getFPUSynonym()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td49 // Mips 32-bit FPU Registers
52 // Mips 64-bit (aliased) FPU Registers
156 /// Mips Single point precision FPU Registers
164 /// Mips Double point precision FPU Registers (aliased
171 /// Mips Double point precision FPU Registers in MFP64 mode.
177 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
430 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
/freebsd-14.2/contrib/file/magic/Magdir/
H A Dolf63 >>36 lelong 1 MathCoPro/FPU/MAU Required
98 >>36 belong 1 MathCoPro/FPU/MAU Required
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.h251 StringRef getFPUSynonym(StringRef FPU);
255 FPUKind parseFPU(StringRef FPU);

1234