1*0b57cec5SDimitry Andric //===-- RegisterContextMach_arm.cpp ---------------------------------------===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric
9*0b57cec5SDimitry Andric #if defined(__APPLE__)
10*0b57cec5SDimitry Andric
11*0b57cec5SDimitry Andric #include "RegisterContextMach_arm.h"
12*0b57cec5SDimitry Andric
13*0b57cec5SDimitry Andric #include <mach/mach_types.h>
14*0b57cec5SDimitry Andric #include <mach/thread_act.h>
15*0b57cec5SDimitry Andric
16*0b57cec5SDimitry Andric
17*0b57cec5SDimitry Andric using namespace lldb;
18*0b57cec5SDimitry Andric using namespace lldb_private;
19*0b57cec5SDimitry Andric
RegisterContextMach_arm(Thread & thread,uint32_t concrete_frame_idx)20*0b57cec5SDimitry Andric RegisterContextMach_arm::RegisterContextMach_arm(Thread &thread,
21*0b57cec5SDimitry Andric uint32_t concrete_frame_idx)
22*0b57cec5SDimitry Andric : RegisterContextDarwin_arm(thread, concrete_frame_idx) {}
23*0b57cec5SDimitry Andric
24*0b57cec5SDimitry Andric RegisterContextMach_arm::~RegisterContextMach_arm() = default;
25*0b57cec5SDimitry Andric
DoReadGPR(lldb::tid_t tid,int flavor,GPR & gpr)26*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) {
27*0b57cec5SDimitry Andric mach_msg_type_number_t count = GPRWordCount;
28*0b57cec5SDimitry Andric return ::thread_get_state(tid, flavor, (thread_state_t)&gpr, &count);
29*0b57cec5SDimitry Andric }
30*0b57cec5SDimitry Andric
DoReadFPU(lldb::tid_t tid,int flavor,FPU & fpu)31*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) {
32*0b57cec5SDimitry Andric mach_msg_type_number_t count = FPUWordCount;
33*0b57cec5SDimitry Andric return ::thread_get_state(tid, flavor, (thread_state_t)&fpu, &count);
34*0b57cec5SDimitry Andric }
35*0b57cec5SDimitry Andric
DoReadEXC(lldb::tid_t tid,int flavor,EXC & exc)36*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) {
37*0b57cec5SDimitry Andric mach_msg_type_number_t count = EXCWordCount;
38*0b57cec5SDimitry Andric return ::thread_get_state(tid, flavor, (thread_state_t)&exc, &count);
39*0b57cec5SDimitry Andric }
40*0b57cec5SDimitry Andric
DoReadDBG(lldb::tid_t tid,int flavor,DBG & dbg)41*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadDBG(lldb::tid_t tid, int flavor, DBG &dbg) {
42*0b57cec5SDimitry Andric mach_msg_type_number_t count = DBGWordCount;
43*0b57cec5SDimitry Andric return ::thread_get_state(tid, flavor, (thread_state_t)&dbg, &count);
44*0b57cec5SDimitry Andric }
45*0b57cec5SDimitry Andric
DoWriteGPR(lldb::tid_t tid,int flavor,const GPR & gpr)46*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteGPR(lldb::tid_t tid, int flavor,
47*0b57cec5SDimitry Andric const GPR &gpr) {
48*0b57cec5SDimitry Andric return ::thread_set_state(
49*0b57cec5SDimitry Andric tid, flavor, reinterpret_cast<thread_state_t>(const_cast<GPR *>(&gpr)),
50*0b57cec5SDimitry Andric GPRWordCount);
51*0b57cec5SDimitry Andric }
52*0b57cec5SDimitry Andric
DoWriteFPU(lldb::tid_t tid,int flavor,const FPU & fpu)53*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteFPU(lldb::tid_t tid, int flavor,
54*0b57cec5SDimitry Andric const FPU &fpu) {
55*0b57cec5SDimitry Andric return ::thread_set_state(
56*0b57cec5SDimitry Andric tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)),
57*0b57cec5SDimitry Andric FPUWordCount);
58*0b57cec5SDimitry Andric }
59*0b57cec5SDimitry Andric
DoWriteEXC(lldb::tid_t tid,int flavor,const EXC & exc)60*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteEXC(lldb::tid_t tid, int flavor,
61*0b57cec5SDimitry Andric const EXC &exc) {
62*0b57cec5SDimitry Andric return ::thread_set_state(
63*0b57cec5SDimitry Andric tid, flavor, reinterpret_cast<thread_state_t>(const_cast<EXC *>(&exc)),
64*0b57cec5SDimitry Andric EXCWordCount);
65*0b57cec5SDimitry Andric }
66*0b57cec5SDimitry Andric
DoWriteDBG(lldb::tid_t tid,int flavor,const DBG & dbg)67*0b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteDBG(lldb::tid_t tid, int flavor,
68*0b57cec5SDimitry Andric const DBG &dbg) {
69*0b57cec5SDimitry Andric return ::thread_set_state(
70*0b57cec5SDimitry Andric tid, flavor, reinterpret_cast<thread_state_t>(const_cast<DBG *>(&dbg)),
71*0b57cec5SDimitry Andric DBGWordCount);
72*0b57cec5SDimitry Andric }
73*0b57cec5SDimitry Andric
74*0b57cec5SDimitry Andric #endif
75