Home
last modified time | relevance | path

Searched refs:DefMI (Results 1 – 25 of 79) sorted by relevance

1234

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp96 if (DefMI->getParent() != MBB) in getAccDefMI()
98 if (DefMI->isCopyLike()) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
113 return DefMI; in getAccDefMI()
149 if (DefMI->getParent() != MBB) in hasLoopHazard()
152 if (DefMI->isPHI()) { in hasLoopHazard()
162 } else if (DefMI->isCopyLike()) { in hasLoopHazard()
165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
179 return DefMI == MI; in hasLoopHazard()
[all …]
H A DARMHazardRecognizer.cpp28 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
39 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
54 MachineInstr *DefMI = LastMI; in getHazardType() local
67 DefMI = &*I; in getHazardType()
71 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
73 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
H A DARMFixCortexA57AES1742098Pass.cpp367 MachineInstr *DefMI = *It; in analyzeMF() local
371 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
378 MachineBasicBlock::iterator DefIt = DefMI; in analyzeMF()
380 if (DefIt != DefMI->getParent()->end()) { in analyzeMF()
381 LLVM_DEBUG(dbgs() << "Moving Fixup to immediately after " << *DefMI in analyzeMF()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp174 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
177 const unsigned InstrLatency = computeInstrLatency(DefMI); in computeOperandLatency()
190 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
201 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
202 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
226 !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() && in computeOperandLatency()
236 return DefMI->isTransient() ? 0 : DefaultDefLatency; in computeOperandLatency()
287 Register Reg = DefMI->getOperand(DefOperIdx).getReg(); in computeOutputLatency()
288 const MachineFunction &MF = *DefMI->getMF(); in computeOutputLatency()
291 return computeInstrLatency(DefMI); in computeOutputLatency()
[all …]
H A DLiveRangeEdit.cpp73 assert(DefMI && "Missing instruction"); in checkRematerializable()
75 if (!TII.isTriviallyReMaterializable(*DefMI)) in checkRematerializable()
91 if (!DefMI) in scanRemattable()
93 checkRematerializable(OrigVNI, DefMI); in scanRemattable()
215 if (DefMI && DefMI != MI) in foldAsLoad()
219 DefMI = MI; in foldAsLoad()
229 if (!DefMI || !UseMI) in foldAsLoad()
234 if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI), in foldAsLoad()
241 if (!DefMI->isSafeToMove(nullptr, SawStore)) in foldAsLoad()
260 DefMI->addRegisterDead(LI->reg(), nullptr); in foldAsLoad()
[all …]
H A DMachineLateInstrsCleanup.cpp131 if (MachineInstr *DefMI = RegDefs[MBB->getNumber()].lookup(Reg)) in clearKillsForDef() local
132 if (DefMI->getParent() == MBB) in clearKillsForDef()
190 for (auto [Reg, DefMI] : RegDefs[FirstPred->getNumber()]) in processBlock()
193 [&, &Reg = Reg, &DefMI = DefMI](const MachineBasicBlock *Pred) { in processBlock()
194 return RegDefs[Pred->getNumber()].hasIdentical(Reg, DefMI); in processBlock()
196 MBBDefs[Reg] = DefMI; in processBlock()
198 << printMBBReference(*MBB) << ": " << *DefMI;); in processBlock()
H A DMachineTraceMetrics.cpp646 const MachineInstr *DefMI; member
651 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
659 DefMI = DefI->getParent(); in DataDep()
788 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
815 if (!Dep.DefMI->isTransient()) in updateDepth()
967 if (!Dep.DefMI->isTransient()) in pushDepHeight()
991 Register Reg = DefMI->getOperand(DefOp).getReg(); in addLiveIns()
1124 addLiveIns(Dep.DefMI, Dep.DefOp, Stack); in computeInstrHeights()
1142 LIR.Height = Heights.lookup(DefMI); in computeInstrHeights()
1194 if (!Dep.DefMI->isTransient()) in getPHIDepth()
[all …]
H A DPHIElimination.cpp165 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); in runOnMachineFunction() local
166 if (!DefMI) in runOnMachineFunction()
177 MachineBasicBlock *DefMBB = DefMI->getParent(); in runOnMachineFunction()
201 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
202 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
205 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
206 DefMI->eraseFromParent(); in runOnMachineFunction()
516 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
517 if (DefMI->isImplicitDef()) in LowerPHINode()
518 ImpDefs.insert(DefMI); in LowerPHINode()
H A DRegisterCoalescer.cpp845 if (!DefMI) in removeCopyByCommutingDef()
847 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
907 if (NewMI != DefMI) { in removeCopyByCommutingDef()
911 MBB->erase(DefMI); in removeCopyByCommutingDef()
1125 if (!DefMI || !DefMI->isFullCopy()) { in removePartialRedundancy()
1305 if (!DefMI) in reMaterializeTrivialDef()
1307 if (DefMI->isCopyLike()) { in reMaterializeTrivialDef()
1365 RM.OrigMI = DefMI; in reMaterializeTrivialDef()
2759 assert(DefMI != nullptr); in analyzeValue()
2876 if (DefMI && in analyzeValue()
[all …]
H A DMachineCSE.cpp186 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
187 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
189 Register SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
192 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
206 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
210 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
221 DefMI->changeDebugValuesDefReg(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
223 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp67 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
141 MachineInstr &DefMI) { in tryToTuneBranch() argument
143 if (MI.getParent() != DefMI.getParent()) in tryToTuneBranch()
149 switch (DefMI.getOpcode()) { in tryToTuneBranch()
195 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
198 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
250 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
253 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
276 DefMI.eraseFromParent(); in tryToTuneBranch()
308 MachineInstr *DefMI = getOperandDef(MI.getOperand(0)); in runOnMachineFunction() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp350 for (auto *DefMI : List) { in chooseBestLEA() local
364 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
371 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
381 BestLEA = DefMI; in chooseBestLEA()
525 MachineInstr *DefMI; in removeRedundantAddrCalc() local
538 DefMI->removeFromParent(); in removeRedundantAddrCalc()
539 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
540 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
543 assert(((InstrPos[DefMI] == 1 && in removeRedundantAddrCalc()
545 InstrPos[DefMI] > in removeRedundantAddrCalc()
[all …]
H A DX86TileConfig.cpp160 for (auto &DefMI : MRI.def_instructions(R)) { in INITIALIZE_PASS_DEPENDENCY() local
161 MachineBasicBlock &MBB = *DefMI.getParent(); in INITIALIZE_PASS_DEPENDENCY()
162 if (DefMI.isMoveImmediate()) { in INITIALIZE_PASS_DEPENDENCY()
165 assert(Imm == DefMI.getOperand(1).getImm() && in INITIALIZE_PASS_DEPENDENCY()
169 Imm = DefMI.getOperand(1).getImm(); in INITIALIZE_PASS_DEPENDENCY()
182 auto Iter = DefMI.getIterator(); in INITIALIZE_PASS_DEPENDENCY()
H A DX86PreTileConfig.cpp222 MachineInstr *DefMI = MRI->getVRegDef(R); in INITIALIZE_PASS_DEPENDENCY() local
223 assert(DefMI && "R must has one define instruction"); in INITIALIZE_PASS_DEPENDENCY()
224 MachineBasicBlock *DefMBB = DefMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
225 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second) in INITIALIZE_PASS_DEPENDENCY()
227 if (DefMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
228 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2) in INITIALIZE_PASS_DEPENDENCY()
229 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB())) in INITIALIZE_PASS_DEPENDENCY()
230 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def. in INITIALIZE_PASS_DEPENDENCY()
232 WorkList.push_back(DefMI->getOperand(I).getReg()); in INITIALIZE_PASS_DEPENDENCY()
234 RecordShape(DefMI, DefMBB); in INITIALIZE_PASS_DEPENDENCY()
H A DX86CallFrameOptimization.cpp611 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
615 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
616 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
617 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
622 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
626 return &DefMI; in canFoldIntoRegPush()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp279 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
281 assert(DefMI); in isCallViaRegister()
285 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
288 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
294 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
295 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
297 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp449 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() local
453 unsigned Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
455 Register SrcReg = DefMI->getOperand(1).getReg(); in getDefSrcRegIgnoringCopies()
459 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
461 Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
629 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; in getOpcodeDef()
789 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() local
790 if (!DefMI) in isKnownNeverNaN()
804 for (const auto &Op : DefMI->uses()) in isKnownNeverNaN()
810 switch (DefMI->getOpcode()) { in isKnownNeverNaN()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp636 if (!DefMI) in simplifyCode()
639 unsigned DefOpc = DefMI->getOpcode(); in simplifyCode()
724 .add(DefMI->getOperand(1)); in simplifyCode()
793 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() local
794 if (!DefMI) in simplifyCode()
796 unsigned DefOpcode = DefMI->getOpcode(); in simplifyCode()
839 LLVM_DEBUG(DefMI->dump()); in simplifyCode()
840 ToErase = DefMI; in simplifyCode()
860 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() local
864 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
[all …]
H A DPPCInstrInfo.h179 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
183 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
189 MachineInstr &DefMI) const;
193 unsigned ConstantOpNo, MachineInstr &DefMI,
208 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
213 const MachineInstr &DefMI,
218 const MachineInstr &DefMI,
325 const MachineInstr &DefMI,
338 const MachineInstr &DefMI, in hasLowDefLatency() argument
483 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
[all …]
H A DPPCVSXSwapRemoval.cpp620 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
621 assert(SwapMap.contains(DefMI) && in formWebs()
623 int DefIdx = SwapMap[DefMI]; in formWebs()
631 LLVM_DEBUG(DefMI->dump()); in formWebs()
725 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
726 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
737 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
756 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval()
[all …]
H A DPPCInstrInfo.cpp174 if (!DefMI.getParent()) in getOperandLatency()
3369 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) in getForwardingDefMI()
3406 if (DefMI) { in getForwardingDefMI()
3418 return DefMI; in getForwardingDefMI()
3687 if (!DefMI) in convertToImmediateForm()
3694 *KilledDef = DefMI; in convertToImmediateForm()
4427 if ((&*It) == &DefMI) in isRegElgibleForForwarding()
4495 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in simplifyToLI()
4784 LLVM_DEBUG(DefMI.dump()); in transformToNewImmFormFedByAdd()
4841 LLVM_DEBUG(DefMI.dump()); in transformToImmFormFedByAdd()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp496 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); in optimizeSelect() local
497 bool Invert = !DefMI; in optimizeSelect()
498 if (!DefMI) in optimizeSelect()
499 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); in optimizeSelect()
500 if (!DefMI) in optimizeSelect()
512 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
515 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
518 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
536 SeenMIs.erase(DefMI); in optimizeSelect()
542 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp726 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); in runOnMachineFunction() local
727 if (DefMI && TII->isFoldableCopy(*DefMI)) { in runOnMachineFunction()
728 const MachineOperand &Def = DefMI->getOperand(0); in runOnMachineFunction()
732 const MachineOperand &Copied = DefMI->getOperand(1); in runOnMachineFunction()
825 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); in processPHINode() local
826 if (DefMI && DefMI->isPHI()) in processPHINode()
827 PHIOperands.insert(DefMI); in processPHINode()
848 MachineInstr *DefMI = MRI->getVRegDef(MaybeVGPRConstMO.getReg()); in tryMoveVGPRConstToSGPR() local
849 if (!DefMI || !DefMI->isMoveImmediate()) in tryMoveVGPRConstToSGPR()
852 MachineOperand *SrcConst = TII->getNamedOperand(*DefMI, AMDGPU::OpName::src0); in tryMoveVGPRConstToSGPR()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h173 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
197 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp578 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
584 switch (DefMI.getOpcode()) { in FoldImmediate()
590 LLVM_DEBUG(DefMI.dump()); in FoldImmediate()
592 assert(DefMI.getOperand(1).isImm()); in FoldImmediate()
593 assert(DefMI.getOperand(2).isImm()); in FoldImmediate()
595 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm()); in FoldImmediate()
601 LLVM_DEBUG(DefMI.dump()); in FoldImmediate()
603 assert(DefMI.getOperand(2).isImm()); in FoldImmediate()
604 if (!DefMI.getOperand(3).isImm()) in FoldImmediate()
607 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm(); in FoldImmediate()
[all …]

1234